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copyright ?2009 by zilog ? , inc. all rights reserved. www.zilog.com product specification ps005308-0609 z80230/z85230/l enhanced serial communications controller
ps005308-0609 do not use in life support life support policy zilog's products are not authorized fo r use as critical components in life support devices or systems without th e express prior written approval of the president and general counsel of zilog corporation. as used herein life support devices or systems are devices which (a) ar e intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordan ce with instructions for use provided in the labeling can be re asonably expected to result in a significant injury to the user. a critical component is any component in a life suppor t device or system whose failure to perform can be reasonably expected to cause the fa ilure of the life support device or system or to affect its safety or effectiveness. document disclaimer ?2009 by zilog, inc. all rights reserved. information in this pu blication concerning the devices, applications, or technology describe d is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. the information contained within this document has been verified accordin g to the general principles of elec trical and mechanical engineering. z8 is a registered trademark of zilog, inc. all ot her product or service names are the property of their respective owners. warning:
ps005308-0609 revision history z80230/z85230/l product specification iii revision history each instance in revision history reflects a change to this docu ment from its previous revision. for more details, re fer to the corresponding pages and appropriate links in the table below. date revision level description page no june 2009 08 removed security watermark from pages all may 2009 07 minor update to page 107 107 may 2009 06 system update change only - no technical content revised n/a mar 2009 05 updated document to add 3v product information removed iso/bsi certif ication information figure 1, 7 and 23 changed 5v to vcc added z8523l dc characteristics updated read and write ac characteristics updated system timing characteristics updated general timing diagram ordering information updated updated standard test conditions updatred table 43 updated table 49 - min value misc ii 2 , 13 , 76 78 90 98 94 107 75 78 98 june 2008 04 updated as per ne w template and style guide. updated figure 4 . all 3 september 2007 03 updated figure 38 and implemented style guide all november 2002 02 editorial updates all august 2001 01 original issue all
ps005308-0609 table of contents z80230/z85230/l product specification iv table of contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin descriptions 1 pins common to both z85230/l and z80230 . . . . . . . . . . . . . . . . . . . . . . . . 4 pin descriptions exclusive to the z85230/l . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin descriptions exclusive to the z80230 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional description 8 input/output capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 escc data communications capabilities . . . . . . . . . . . . . . . . . . . . . . . . . 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . z80230/z85230/l enhancements 22 4-byte transmit fifo buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8-byte receive fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 write register 7 prime (wr7?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 crc reception in sdlc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 txd forced high in sdlc with nrzi encoding when marking idle . . . . . . 26 improved transmit interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 dpll counter tx clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 read register 0 status latched during read cycle . . . . . . . . . . . . . . . . . 27 software interrupt acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 fast sdlc transmit data interrupt response . . . . . . . . . . . . . . . . . . . . . . 28 sdlc fifo frame status enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . 28 fifo enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 fifo read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 fifo write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 sdlc status fifo anti-lock feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . programming 32 initializing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 read registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . z80230 interface timing 70 z80230 write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 z80230 read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 z80230 interrupt acknowledge cycle timing . . . . . . . . . . . . . . . . . . . . . . . 71 z85230/l timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 z85230/l read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
ps005308-0609 table of contents z80230/z85230/l product specification v z85230/l write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 z85230/l interrupt acknowledge cycle timing . . . . . . . . . . . . . . . . . . . . . . 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . electrical characteristics 75 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 standard test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 z85230/l ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . z80230/z85230/l errata 99 ius problem description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 ius problem solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 rts problem description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 rts problem solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 automatic txd forced high problem description . . . . . . . . . . . . . . . . . . . 102 automatic txd forced high problem solutions . . . . . . . . . . . . . . . . . . . . 103 sdlc fifo overflow problem description . . . . . . . . . . . . . . . . . . . . . . . . 103 sdlc fifo overflow problem solution . . . . . . . . . . . . . . . . . . . . . . . . . . 103 default rr0 value problem description . . . . . . . . . . . . . . . . . . . . . . . . . . 103 default rr0 value problem solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 default rr10 value problem description . . . . . . . . . . . . . . . . . . . . . . . . . 104 default rr10 value problem solution . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 crc problem description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 crc problem solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package information 105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ordering information 107 z8523l (3.3v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 z85230 (5v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 part number suffix designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ps005308-0609 pin descriptions z80230/z85230/l product specification 1 pin descriptions the enhanced serial co mmunication controller (escc) pins are divided into seven func - tional groups: 1. address/data 2. bus timing and reset 3. device control 4. interrupt 5. serial data (both channels) 6. peripheral control (both channels) 7. clocks (both channels) figure 1 on page 2 and figure 2 on page 2 display the pins in each functional group for both the z80230 and z85230/l . the pin functions are unique to each bus interface version in the address/data group, bus timing a nd reset group, and device control group. the address/data group consists of the bidirec tional lines used to transfer data between the cpu and the escc (addresses in the z80230 are latched by as ). the direction of these lines depends on whether the opera tion is a read or a write operation. the timing and control groups designate the type of transaction to occur and the timing of the occurrence. the interrupt group provides inputs and outputs for handling and prior - itizing interrupts. the remainin g groups are divided into ch annel a and channel b groups for: ? serial data (transmit or receive) ? peripheral control (such as dma or modem) ? input and output line for the receive and transmit clocks
ps005308-0609 pin descriptions z80230/z85230/l product specification 2 figure 1. z85230/l pin functions figure 2. z80230 pin functions txda rxda trxca rtxca synca w /reqa dtr /reqa rtsa ctsa dcda txdb rxdb trxcb rtxcb syncb w /reqb dtr /reqb rtsb ctsb dcdb d7 d6 d5 d4 d3 d2 d1 d0 rd wr a/b ce int intack iei ieo d/c z85230/l serial data channel clocks channel controls for modem, dma and other channel controls for modem, dma and other channel clocks serial data data bus bus timing and reset control interrupt channel a channel b +vccgnd pclk txda rxda trxca rtxca synca w /reqa dtr /reqa rtsa ctsa dcda txdb rxdb trxcb rtxcb syncb w /reqb dtr /reqb rtsb ctsb dcdb ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 as ds r/w cs1 int intack iei ieo cs0 z80230 serial data channel clocks channel controls for modem, dma and other channel controls for modem, dma and other channel clocks serial data data bus bus timing and reset control interrupt channel a channel b + v cc gnd pclk
ps005308-0609 pin descriptions z80230/z85230/l product specification 3 figure 3 displays the z85230/l dip and plcc pin assignments, respectively. figure 4 displays the z80230 dip and plcc pin assignments. figure 3. z85230/l pin assignments figure 4. z80230 pin assignments d1 d3 d5 d7 int ieo iei intack vcc w /reqa synca rtxca rxda trxca txda dtr /reqa rtsa ctsa dcda pclk 1 20 d0 d2 d4 d6 rd wr a/b ce d/c gnd w /reqb syncb rtxcb rxdb trxcb txdb dtr /reqb rtsb ctsb dcdb 40 21 z85230 z85230 dip pin assignments 7 39 29 17 18 28 ieo iei intack vcc w /reqa synca rtxca rxda trxca txda n/c z85230/l plcc pin assignments a/b ce d/c n/c gnd w /reqb syncb rtxcb rxdb trxcb txdb n/c dtr /reqa rtsa ctsa dcda pclk dcdb ctsb rtsb dtr /reqb n/c int d7 d5 d3 d1 d0 d2 d4 d6 rd wr z85230/l 6 1 40 ad1 ad3 ad5 ad7 int ieo iei intack vcc w /reqa synca rtxca rxda trxca txda ctsa dcda 1 20 ad0 ad2 ad4 ad6 ds as r/w cs0 cs1 gnd w /reqb syncb rtxcb rxdb trxcb txdb dtr /reqb rtsb ctsb dcdb 40 21 z80230 z80230 dip pin assignments 61 40 39 29 7 17 18 28 ieo iei intack vcc w /reqa synca rtxca rxda trxca txda n/c z80230 plcc pin assignments r/w cs0 cs1 n/c gnd w /reqb syncb rtxcb rxdb trxcb txdb n/c dtr /reqa rtsa ctsa dcda pclk dcdb ctsb rtsb dtr /reqb n/c int ad7 ad5 ad3 ad1 ad0 ad2 ad4 ad6 ds as z80230 rtsa pclk dtr /reqa
ps005308-0609 pin descriptions z80230/z85230/l product specification 4 pins common to both z85230/l and z80230 the pin descriptions for pins common to both z85230/l and z80230 are provided below: ctsa , ctsb (clear to send (inputs, active low))? these pins function as transmitter enables if they are programmed for auto enable (wr3 bit 5 is 1), in which case a low on each input enables the respective transmitter. if not programmed as auto enable , the pins may be used as general-purpo se inputs. these pins are schmitt-trigger buffered to accommodate slow rise-time inputs. the escc detects pulses on these pins and may interrupt the cpu on both logic level transitions. dcda , dcdb (data carrier detect (inputs, active low))? these pins function as receiver enables if they are programmed for auto enable (wr3 bit 5 is 1); otherwise, they are used as general-purpose input pins. the pins are schmitt-trigger buffered to accommodate slow rise-time signals. the escc detects pulses on these pins and may interrupt the cpu on both logic level transitions. rtsa , rtsb (request to send (outputs, active low))? the rts pins can be used as general-purpose outputs or with the auto enable feature. when auto-enable is off, these pins follow the inverse state of wr5 bit 1. when u sed with the auto- enable feature in asynchronous mode, this pin immediately goes low when wr5 bit 1 is 1. when wr5 bit 0 is 0, this pin remains low until the transmitter is empty. in synchronous data link control (sdlc) mode, the rts pins can be programmed to be deasserted when the closing flag of the message clears the txd pin, if wr7? bit 2 is 1, wr10 bit 2 is 0, and wr5 bit 1 is 0. synca , syncb (synchronization (inputs or outputs, active low))? these pins can act either as inputs, outputs, or as part of the crystal oscillator circuit. in the asynchro - nous receive mode (crystal oscillator option not selected), these pins are inputs simi - lar to cts and dcd . in this mode, transition on these lines affect the state of the sync/ hunt status bits in read register 0 but have no other function. in external synchronization mode, with the crystal oscillator not selected, these lines also act as inputs. in this mode, sync is driven low, two rx clock cycles after the last bit of the sync character is received. character assembly begins on the rising edge of the receive clock immedi ately preceding the activation of sync . in the internal synchronization mode (monosync and bisync) with the crystal oscillator not selected, these pins act as outputs. th ese outputs go low each time a sync pattern is recognized, regardless of character boundaries. in sdlc mode, pins switch from input to output when monosy nc, bisync, or sdlc is programmed in wr4 and sync modes are enabled. dtr /reqa , dtr /reqb (data terminal ready/request (output, active low))? these pins can be programmed (wr14 bit 2) to serve either as general-purpose outputs or as dma request lines. when programmed for dtr function (wr14 bit 2 is 0), these out - puts follow the inverse of the dtr bit of write register 5 (wr5 bit 7). when pro - grammed for request mode these pins serv e as dma requests for the transmitter.
ps005308-0609 pin descriptions z80230/z85230/l product specification 5 when used as dma request lin e (wr14 bit 2 is 1), the timing for the deactivation request can be programmed in write register 7 ? (wr7?) bit 4. if this bit is 1, the dtr / req pin is deactivated with the same timing as the w / req pin. if 0, the deactivation timing of dtr / req pin is four clock cycles, th e same as in the z80c30/z85c30. w /reqa , w /reqb (wait/request (output, open-drain when programmed for wait function, driven high and low when programmed for request function))? these dual-purpose outputs may be programmed as request lines for a dma controller or as wait lines to synchronize th e cpu to the escc data rate. the reset state is wait. rxda, rxdb (receive data (inputs, active high))? these inputs receive serial data at standard transistor-transistor logic (ttl) levels. rtxca , rtxcb (receive/transmit clocks (input, active low))? these pins can be programmed to several modes of operation. in each channel, rtxc may supply the fol - lowing: ? receive clock and/or the transmit clock ? clock for the baud rate generator (brg) ? clock for the digital phase-locked loop these pins can also be programm ed for use with the respective sync pins as a crystal oscillator. the receive clock ma y be 1, 16, 32, or 64 times the data rate in asynchro - nous modes. txda, txdb (transmit data (output, active high))? these output transmit serial data at standard ttl levels. trxca , trxcb (transmit/receive clocks (input or output, active low))? these pins can be programmed in several different modes. when configured as an input, the trxc may supply the receive clock and/or the transmit clock. when configured as an out - put, trxc can echo the clock output of the digital phase-locked loop, the crystal oscilla - tor, the brg or the transmit clock. pclk (clock (input))? this clock is the master escc cloc k used to synchronize internal signals. pclk is a ttl level signal. pclk is not required to have any phase relationship with the master system clock. iei (interrupt enable in (input, active high))? iei is used with ieo to form an interrupt daisy chain when there is more than one inte rrupt-driven device. a high iei indicates that no higher priority device has an interrupt under service (ius) or is requesting an ? interrupt. ieo (interrupt enable out (output, active high))? ieo is high only if iei is high and the cpu is not servicing an escc interrupt. during an inte rrupt acknowledge cycle, ieo is also driven low if the escc is requestin g an interrupt. ieo can be connected to the next lower priority device?s iei input, and in this case inhibits interrupts from lower prior - ity devices.
ps005308-0609 pin descriptions z80230/z85230/l product specification 6 int (interrupt (output, open-drain, active low))? this pin activates when the escc requests an interrupt. the int is an open-drain output. intack (interrupt acknowledge (input, active low))? this pin is a strobe which indi - cates that an interrupt acknowledge cycle is in progress. during this cycle, the escc interrupt daisy chain is resolved. the device ca n return an interrupt vector that may be encoded with the type of interrupt pending. during the acknowledge cycle, if iei is high, the escc places the interrupt ve ctor on the data bus when rd goes active for the z85230/ l, or when ds goes active for the z80230. intack is latched by the rising edge of pclk. pin descriptions excl usive to the z85230/l the pin description for pins exclusive to z85230/l is provided below: pins d7?d0 (data bus (bidirectional, tristate))? these pins carry data and commands to and from the z85230/l. ce (chip enable (input, active low))? this pin selects the z85230/l for a read or write operation. rd ((read (input, active low))? this pin indicates a read operation and, when the z85230/l is selected, enables the z85230/l?s bus drivers. during the interrupt acknowl - edge cycle, rd gates the interrupt vector onto the bu s if the z85230/l is the highest prior - ity device reques ting an interrupt. wr (write (input, active low))? when the z85230/l is selec ted, this pin denotes a write operation, which indicat es that the cpu writes command bytes or data to the z85230/l write registers. wr and rd going low simultaneously is interpreted as a reset. a/b (channel a/channel b (input))? this pin selects the channe l in which the read or write operation occurs. a high selects channel a and a low selects channel b. d/c (data/control select (input))? this signal defines the ty pe of information trans - ferred to or from the z85230/l. a high indicat es data transfer and a low indicates a com - mand transfer. pin descriptions exclusive to the z80230 the pin description for pins exclusive to z80230 is provided below: ad7?ad0 (address/data bus (bidirectional, active high, tristate))? these multi - plexed lines carry register addresses to the z 80230 as well as data or control information to and from the z80230. r/w (read/write (input, read active high))? this pin specifies if the operation to be performed is a read or write operation. note:
ps005308-0609 pin descriptions z80230/z85230/l product specification 7 cs0 (chip select 0 (input, active low))? this pin is latched co ncurrently with the addresses on a7-a0 and must be low fo r the intended bus transaction to occur. cs1 (chip select 1 (input, active high))? this second chip select pin must be high before and during the intended bus transaction. ds (data strobe (input, active low))? this pin provides timing for the transfer of data into and out of the z80230. if as and ds are both low, this cond ition is interpreted as a reset. as (address strobe (input, active low))? addresses on a7-a0 are latched by the ris - ing edge of this signal.
ps005308-0609 functional description z80230/z85230/l product specification 8 functional description the architecture of the escc is descr ibed based on its functionality as a: ? data communications device, which transmits and receives data in a wide variety of protocols ? microprocessor peripheral, in which the escc offers valuable features such as vectored interrupts and dma support the details of the communicatio n between the receive and tran smit logic of the system bus are displayed in figure 5 and figure 6 on page 9 . the features and data path for each of the escc a and b channels are identical. for more information on scc/escc and iscc family of products, refer to the respective user manuals available for download from www.zilog.com . figure 5. escc transmit data path wr7 wr6 sync register 20-bit tx shift register zero insert crc-sdlc crc-gen from receiver sync register internal data bus wr8 tx fifo internal txd async sync sdlc transmit clock final tx mux nrzi encode transmit mux and 2 bit delay txd to other channel 4 bytes
ps005308-0609 functional description z80230/z85230/l product specification 9 figure 6. escc receive data path input/output capabilities system communication to and from th e escc is accomplished using the ? escc register set. there are 17 write registers and 16 read registers. many of the fea - tures on the escc are enabled through a new register in the escc: write register 7 prime (wr7?). this new register can be accessed if bit 0 or wr15 is set to 1. table 1 on page 10 lists the write registers and a br ief description of their functions. table 2 on page 11 lists the read registers. rec. error logic cpu i/o i/o data buffer internal data bus upper byte (wr13) time constant lower byte (wr12) time constant brg input 16 bit down counter div 2 brg output status fifo 10 x 19 frame rx data fifo 8 bytes deep rx error fifo 8 bytes deep hunt mode (bisync) 14 bit counter dpll in dpll internal txd rxd 1 bit mux nrzi and 0 delete sync register decode mux out receive shift register 3 bits crc delay register (8 bits) crc checker sdlc-crc crc result sync crc to transmit section dpll
ps005308-0609 functional description z80230/z85230/l product specification 10 throughout this document the write and read registers are referenced with the notations wr for write register and rr for read register. for example: wr4a ? write register 4 for channel a rr3 ? read register 3 for either or both channels table 1. escc write registers write register functions wr0 command register; select sh ift left/right mode, cyclic redundancy check (crc) initia lization, and resets for various modes wr1 interrupt conditions, wait/dma request control wr2 interrupt vector, accessed through either channel wr3 receive and miscellaneous control parameters wr4 transmit and receive parameters and modes wr5 transmit parameters and controls wr6 sync character or sdlc address field wr7 sync character or sdlc flag wr7? sdlc enhancements enable, a ccessible if wr15 bit d0 is 1 wr8 transmit fifo, 4-bytes deep wr9 reset commands and master int enable, accessible through either channel wr10 miscellaneous transmit and receive controls wr11 clock mode control wr12 lower byte of brg time constant wr13 upper byte of brg time constant wr14 miscellaneous controls and digital phase-locked loop (dpll) commands wr15 external interrupt control note:
ps005308-0609 functional description z80230/z85230/l product specification 11 there are three modes used to move data into and out of the escc: 1. polling 2. interrupt (vectored and non-vectored) 3. block transfer the block transfer mode can be impl emented under cpu or dma control. polling when polling, data interrupts are disabled , three registers in the escc are automati - cally updated when ever any function is performed. fo r example, end-of-frame (eof) in sdlc mode sets a bit in one of these status registers. the purpose of polling is for the cpu to periodically read a status register until the register contents indicate the need that data requires transfer. rr0 is the only register that must be read to determine if data needs to be transferred. an altern ative to polling rr0 for each ch annel is to poll the interrupt table 2. escc read registers register name functions rr0 transmit, receive, and external status rr1 special receive condition status bits rr2a unmodified interrupt vector rr2b modified interrupt vector rr3a interrupt pending bits rr4 wr4 mirror, if wr7? bit d6 equals 1 rr5 wr5 mirror, if wr7? bit d6 equals 1 rr6 sdlc frame lsb byte count, if wr15 bit d2 equals 1 rr7 sdlc frame 10 x 19 fifo stat us and msb byte count, if wr15 bit ds equals 1 rr8 receive data fifo, 8 bits deep rr9 wr9 mirror, if wr7? bit d6 equals 1 rr10 miscellaneous status bits rr11 wr11 mirror, if wr7? bit d6 equals 1 rr12 lower byte of brg time constant rr13 upper byte of brg time constant rr14 wr14 mirror, if wr7? bit d6 equals 1 rr15 wr 15 mirror, if wr7? bit d6 equals 1
ps005308-0609 functional description z80230/z85230/l product specification 12 pending register. status information for both channels resides in one register. only one register may be read. depending on its cont ents, the cpu performs one of the three opera - tions listed below: 1. write data 2. read data 3. continues processing two bits in the register indicate the requirement for data transfer. interrupt the escc interrupt mode supports vectored an d nested interrupts. the fill levels at which the transmit and receive fifos interrupt the cpu are programmable, allowing the escc requests for data transfer to be tu ned to the system in terrupt response time. nested interrupts are supported w ith the interrupt acknowledge ( intack ) feature of the escc. it allows the cpu to acknowledge th e occurrence of an interrupt, and re-enable higher priority interrupts. since an intack cycle releases the int pin from the active state, a higher priority escc interrupt or anot her higher priority device can interrupt the cpu. when an escc responds to intack signal from the cpu, it can place an interrupt vector on the data bus. this vector is writte n in wr2 and may be read in rr2. to increase the interrupt response time, the escc can modify 3 bits in this vector to indicate status. if the vector is read in channel a, status is not included. if it is read in channel b, status is included. each of the six sources of interrupts in the escc (transmit, receive, and external/status interrupts in both channels) ha s 3 bits associated with the interrupt source as listed below: 1. interrupt pending (ip) 2. interrupt under service (ius) 3. interrupt enable (ie) if the ie bit is set for a given interrupt sour ce, then that source can request interrupts. however, when the master interrupt enable (mie) bit in wr9 is reset, no interrupts can be requested. the ie bits are write-only. the ot her two bits are related to the interrupt pri - ority chain (see figure 7 on page 13 ). the escc can request an interrupt only when no higher priority device is reques ting an interrupt (that is, when iei is high). if the device in question requests an interrupt, it pulls down int . the cpu then responds with intack , and the interrupting device plac es a vector on the data bus.
ps005308-0609 functional description z80230/z85230/l product specification 13 figure 7. escc interrupt priority schedule the escc can also execute an interrupt ackn owledge cycle using software. sometimes it is difficult to create the intack signal with the necessary timing to acknowledge inter - rupts and allow the nesting of interrupts. in such cases, interrupts can be acknowledged with a software comm and to the escc. for more information, z80230/z85230/l enhancements on page 22 interrupt pending (ip) bits signal a need for interrupt servicing. when an ip bit is 1 and the iei input is high, the int output is pulled low, requesting an interrupt. in the escc, if an ie bit is not set, then the ip for that source is never set. the ip b its are read in rr3a. the interrupt under service (ius) bits signal that an interrupt request is serviced. if ius is set to 1, all interrupt sources of low priority in the escc and external to the escc are pre - vented from requesting interrupts. the internal interrupt sources are inhibited by the state of the internal daisy chain, while lower prio rity devices are inhibited by setting ieo low for subsequent peripherals. an ius bit is set during an interrupt acknowledge cycle if there are no higher priority devices requesting interrupt. there are three type of interrupts as listed below: 1. transmit 2. receive 3. external/status each interrupt type is enabled under program control with channel a having higher prior - ity than channel b, and with tran smit, receive, and external/status interrupts prioritized in that order within each chan nel. when the transmit interrupt is enabled (wr1 bit 1 is 1), the occurrence of the interrupt depends on the state of wr7? bit 5. if wr7? bit 5 is 0, the cpu is interrupted when the top byte of th e transmit first in firs t out (fifo) becomes empty. if wr7? bit 5 is 1, the cpu is inte rrupted when the transmit fifo becomes com - pletely empty. the transmit interrupt occurs when the data in the exit location of the transmit fifo loads into the transmit shif t register and the transmit fifo becomes completely empty. this conditio n means that there must be at least one character written to the tx fifo for it to become empty. peripheral peripheral peripheral iei a7?a0int intack ieo iei a7?a0 int intack ieo iei a7?a0int intack + v cc a7?a0 int intack +v cc
ps005308-0609 functional description z80230/z85230/l product specification 14 when the receiver is enabled, the cpu is interrupted in one of the following three meth - ods: 1. interrupt on first receive character or special receive condition 2. interrupt on all receive charact ers or special receive conditions 3. interrupt on special receive conditions only if wr7? bit 3 is 1, and the special receive condition is sel ected, the receive character occurs when there are four bytes available in the receive fifo. this is most useful in syn - chronous applications as the data is in consec utive bytes. interrupt on first character or special condition and interrupt on special co ndition only are typically used with the block transfer mode. a spec ial receive condition consists of one of the follow - ing: ? receiver overrun ? framing error in asynchronous mode ? eof in sdlc mode ? parity error (optional) the special receive condition interrupt is di fferent from an ordinary receive character available interrupt only by the status placed in the vector during the interrupt acknowl - edge cycle. in receive interru pt on first character or spec ial condition mode, an inter - rupt occurs from spec ial receive conditions any time after the first receive character interrupt. the primary function of the extern al/status interrupt is to mon itor the signal transitions of the cts , dcd , and sync pins. however, an external/sta tus interrupt is also caused by any of the following: ? a transmit underrun condition ? a zero count in the brg ? a detection of a break (asynchronous mode) ? an abort (sdlc mode) ? an end of poll (eop) sequence in the data stream (sdlc loop mode) the interrupt caused by the abort or eop se quence has a special feature that allows the escc to interrupt when the abort or eop seque nce is detected or terminated. this fea - ture facilitates the proper term ination of the current message, correct initialization of the next message, and the accurate timing of the abort condition by external logic in sdlc mode. sdlc loop mode allows secondary sta tions to recognize the primary station and regain control of the lo op during a poll sequence.
ps005308-0609 functional description z80230/z85230/l product specification 15 cpu/dma block transfer the escc provides a block transfer mode to accommodate cpu/dma controller. the block transfer mode uses the wa i t / request output in conjunction with the wa i t / request bits in wr1. the wa i t / request output can be defined as a wa i t line in the cpu block transfer mode or as a request line in the dma block transfer mode. to a dma controller, the escc request output indicates that the escc is ready to transfer data to or from memory. to the cpu, the wa i t line indicates that the escc is no t ready to transfer data, thereby requesting the cpu to extend the i/o cycle. the dtr / request line allows full-duplex opera tion under dma control. the escc can be programmed to deassert the dtr / request pin with the sam e timing as the wa i t / request pin if wr7? bit 4 is 1. escc data communications capabilities the escc provides two independent full-duplex programmable channels for use in any common asynchronous or synchronous data communication protocols (see figure 8 ). the channels have iden tical features and capabilities. figure 8. various escc protocols marking line start parity stop data asynchronous sync crc1 crc2 monosync bisync signal flag address control information flag crc2 crc2 crc2 crc1 crc1 crc1 sync sync data data data data data data data data marking line external sync sdlc/hdlc/x.25
ps005308-0609 functional description z80230/z85230/l product specification 16 asynchronous mode the escc has significant improvements over the standard serial communications con - troller (scc). the addition of the deeper da ta fifos provide greater protection against underruns and overruns as well as more effici ent use of bus bandwidth. the deeper data fifos are accessible regardless of the protocol used and they need not be enabled. for information on these improvements, see z80230/z85230/l enhancements on page 22 send and receive allow 5 to 8 bits per charac ter, plus optional even or odd parity. the transmitters can supply 1, 1.5, or 2 stop b its per character and can provide break indica - tion. the receiver break-detectio n logic interrupts the cpu both at the start and at the end of a received break. reception is protected fro m spikes by start-bit va lidation that delays the signal for a length of time equal to one half the time period required to process 1 bit of data after a low level is det ected on the receive data input (rxda or rxdb pins). if the low level does not persist (that is, a transi ent), the character assembly process does not start. framing errors and overrun errors are detected and buffered together with the character at which they occur. vectored interrupts allow fast servicing of error conditions. further - more, a built-in checking process avoids the in terpretation of a framing error as a new start bit. a framing error results in the addition of a delay of one half the am ount of time required to process 1 bit of data at the poin t at which the search for the next start bit begins. transmit and receive clock can be selected from any of the several sources. in asynchronous mode, the sync pin may be programmed as an input with interrupt capability. synchronous mode the escc supports both byte-oriented and bit-oriented synchronous communica - tion. synchronous byte-oriented protocols are handled in several modes. they enable character synchronization with a 6- or 8-bit sync character (monosync) or a 12-bit or 16-bit synchronization pattern (bisyn c), or with an external sync signal. lead - ing sync characters are remove d without interrupting the cpu. 5- or 7-bit sync characters are detected from 8- or 16-bit patterns in the escc by overlap - ping the larger pattern across multiple inco ming sync characters as displayed in figure 9 . figure 9. detecting 5- or 7-bit synchronous characters sync data sync sync data data data 5 bits 8 16
ps005308-0609 functional description z80230/z85230/l product specification 17 crc checking for synchronous byte-oriented mode is delayed by one charac - ter time so that the cpu may disable crc checking on specific characters. this action permits the implementation of protocols such as ibm bisync. both crc-16 (x 16 + x 15 + x 2 + 1) and crc-ccitt (x 16 + x 12 + x 5 + 1) error checking polynomials are supporte d. either polynomial may be selected in all synchronous modes. you can preset the crc generator and checker to all 1s or all 0s. th e escc also provides a feature that automatically transmits crc data when no other data is available for trans - mission. this feature enables high-speed tran smissions under dma cont rol, with no need for cpu intervention at the end of a message. when there is no data or crc to send in the synchronous mode, the transmitter inserts 6- , 8-, 12-, or 16-bit sync characters, regardless of the programmed character length. sdlc mode the escc supports synchronous bit-oriented protocols, such as sdlc and ? high-level data link control (hdlc), by pe rforming automatic flag sending, zero inser - tion, and crc generation. a special command is used to abort a frame wh ich is in transmission. at the end of a mes - sage, the escc automatically transmits the crc and trailing flag when the transmitter underruns. the transmitter may al so be programmed to send an idle line consisting of con - tinuous flag characters or a steady marking condition. if a transmit underrun occurs in the middle of a message, an external/status interrupt warns the cpu of this stat us change so that an abort command can be issued. the escc may also be programmed to send an abort command by itself, in the event of an ? underrun, relieving the cpu of th e task. the last character of a frame may consist of 1- to 8-bits, allowing reception of frames of any length. the receiver automatically sync hronizes on the leading flag of a frame in sdlc or hdlc and provides a synchronization signal on the sync pin (an interrupt may also be pro - grammed). the receiver may search for frames addressed by 1-byte or 4-bits within a byte of a user-specified address or for a global br oadcast address. frames not matching either the user-selected address or broadcast address are ignored. the number of address bytes are extended un der software control. to receive data, an interrupt can be selected on the first received character, or on every character, or on spe - cial condition only (eof). the receiver automa tically deletes all zeros inserted by the transmitter during character assembly. crc is also calculated and is automatically checked to validate frame transm ission. at the end of transmissi on, the status of a received frame is available in the status registers. in sdlc mode, the escc must be programmed to use the crc-ccitt polynomial, but the generator and checker may be pre-set to all 1s or all 0s. the crc data is inverted before tr ansmission and the receiver checks against the bit pattern 0001110100001111 .
ps005308-0609 functional description z80230/z85230/l product specification 18 nrz, nrzi, or fm coding may be used in any 1x mode. the parity options available in asynchronous mode are also available in synchronous mode. however, parity checking is not normally used for sdlc because crc checking is more robust. sdlc loop mode the escc supports sdlc loop mode as we ll as normal sdlc. in sdlc loop mode, a primary controller station manages the message traffic flow on the loop and any number of secondary stations. in sdlc loop mode , the escc performs the functions of a sec - ondary station. an escc operation in regu lar sdlc mode may act as a controller (see figure 10 ). sdlc loop mode is selected by setting wr10 bit 1 to 1. figure 10. sdlc loop mode a secondary station in an sdlc loop mode always monitors the messages sent around the loop and passes these messag es to the rest of the loop, re transmitting them with a one- bit time delay. the secondary station places its own message in the loop only at specific times. the controller indicat es that the secondary stations can transmit messages by send - ing a special character, called eop, around the loop. the eop character has a bit pattern 11111110 , the same pattern as an abort character in normal hdlc. this bit pattern is unique and easily recognized, because of the zero insertion in the message. when a secondary station has a message to transmit and recognizes an eop on the line, it changes the last binary 1 of the eop to a 0 before transmission. this action changes the eop into a flag sequence. the secondary stat ion now places its message on the loop and terminates the message with an eop. any seco ndary stations further down the loop with messages to transmit appends their messages to the message of the first secondary station using the same process. secondary stations without any messages to transmit merely echo the incoming message. all secondary stations are prohibited from plac ing messages on the loop except upon recognizing an eop. in sdlc loop mode, nrz, nrzi or fm coding can be used. controller secondary #1 secondary #2 secondary #3 secondary #4
ps005308-0609 functional description z80230/z85230/l product specification 19 sdlc status fifo the escc?s ability to receive high speed back -to-back sdlc frames is maximized by a 10-bit deep by 19-bit wide status fifo buffer. when enabled (through wr15 bit 2 is 1), the storage area enables dma to continue data transfer into the memory, so that the cpu examines the message later. for each sdlc frame , 14 counter bits and 5 status/error bits are stored. the byte count and status bits ar e accessed through read registers, rr6, and rr7. rr6 and rr7 are only used when the sdlc fifo buffer is enabled. the 10 x 19 status fifo buffer is separate from the 8-byte receive data fifo buffer. baud rate generator each channel in the escc contains a progra mmable brg. each genera tor consists of two 8-bit registers that form a 16-bit time consta nt, a 16-bit down counter, and a flip-flop on the output, producing a square wave. at start-up , the flip-flop at the output is set high, the value in the time constant regist er is loaded into the counte r, and the count down begins. when the brg reaches zero, the ou tput toggles, the counter is reloaded with the time con - stant, and the process repeats. the time cons tant can be changed at any time, but the new value does not take effect unti l the counter is loaded again. the output of the brg may be used as the tran smit clock, the receive clock, or both. the output can also drive the dpll. for more information, see digital phase- locked loop . if the receive clock or the transmit clock is not programmed to come from the trxc pin, the output of the brg may be echoed out by the trxc pin. the following formula rela tes the time constant to the baud rate. pclk or rtxc is the clock input to the brg. the clock mode is 1, 16, 32, or 64, as selected in wr 4 bits 6 and 7. digital phase-locked loop the escc contains a dpll to recover clock info rmation from a data stream with nrzi or fm encoding. the dpll is driven by a cloc k that is nominally 32 (nrzi) or 16 (fm) times the data rate. the dpll uses this clock, along with the data stream, to construct a clock for the data. this clock is then used as the escc receive clock, the transmit clock, or both. when the dpll is selected as the transmit clock source, it provides a jitter-free clock output. the clock output is the dpll input frequency divided by the appropriate divisor for the selected encoding technique. for nrzi encoding, the dpll co unts the 32x clock to creat e nominal bit times. as the 32x clock is counted, the dpll searches the incoming data st ream for edges (either 1 to 0 or 0 to 1). when a transition is detected the dpll makes a count adjustment (during the next counting cycle), producing a terminal co unt closer to the center of the bit cell. pclk or rtxc frequency time constant = 2(baud rate) (clock mode) -2
ps005308-0609 functional description z80230/z85230/l product specification 20 for fm encoding, the dpll counts from 0 to 32, but with a cycle corresponding to two bit times. when the dpll is locked, the clock edges in the data stream occurs between counts 15 and 16 and between counts 31 and 0. the dpll looks for edges only during a time centered on the 15 to 16 counting transition. the 32x clock for the dpll can be programmed to come from either the rtxc input or the output of the brg. the dpll output is pr ogrammed to be echoed out the escc by the trxc pin (if this pin is no t being used as an input). data encoding data encoding allows the tr ansmission of clock and data information over the same medium. this capability saves th e need to transmit clock and data over separate medium as is normally required tor synchronous data. the escc provides four different data encoding methods, selected by bits 6 and 5 in wr10. examples of these 4 encoding meth - ods is displayed in figure 11 . any encoding method is used in any x1 mode in the escc, asynchronous or synchronous. the data encoding selected is active even if the transmitter or receiver is idling or disabled. figure 11. data encoding methods table 3 lists the four encoding meth ods, their levels, and values. table 3. data encoding descriptions code type level value nrz high low 1 0 nrzi no change change 1 0 data nrz nrzi fm1 fm0 110010
ps005308-0609 functional description z80230/z85230/l product specification 21 in addition to the four methods, escc can be used to decode manchester (biphase level) data using dpll in the fm mode and prog ramming the receiver for nrz data. man - chester encoding always produces a transition at the center of the bit cell. if the transition is 0 to 1, the bit is a 0. if the tr ansition is 1 to 0, the bit is a 1. auto echo and local loopback the escc is capable of automatically echoing everything it receives. this feature is use - ful mainly in asynchronous modes, but works in synchronous and sdlc modes as well. auto echo mode (txd is rxd) is used with nrzi or fm encoding with an additional delay becaus e the data stream is not deco ded before retransmission. in auto echo mode, the cts input is ignored as a tran smitter enable, (although transi - tions for this input can cause interrupts if prog rammed to do so). in this mode, the trans - mitter is actually bypassed and the progra mmer is responsible for disabling transmitter interrupts and wait / request on transmit. the escc is also capable of local loopba ck. in this mode th e internal transmit data is tied to the internal rece ive data and rxd is ignored. the cts and dcd inputs are also ignored as transmit and receive enables. however, transitions on these inputs can cause interrupts. local loopback works in asynchronous, synchro - nous, and sdlc modes with nrz, nrzi, or fm coding of the data stream. fm1 (biphase mark) additional transition at the center of the bit cell no additional transition at the center of the bit cell 1 0 fm0 (biphase space) a transition occurs at the beginning of every bit call. a 0 is represented by an additional transition at the center of the bit cell. a 1 is represented by no additional transition at the center of the bit cell. 0 1 table 3. data encoding descriptions (continued) code type level value
ps005308-0609 z80230/z85230/l enhancements z80230/z85230/l product specification 22 z80230/z85230/l enhancements a detailed description of the enhancements to the z80230/z85230/l escc that differenti - ate it from the standard scc is provided below: 4-byte transmit fifo buffer the escc has a 4-byte transmit buffer with programmable interrupt and dma request levels. it is not necessary to enable the fifo buffer as it is always available. you can set the transmit buffer empty (tbe) interrupt and dma request on transmit command to be generated either when the top byte of transmit fifo is empty or only when the fifo is completely empty. a hardware or channel reset clears the transmit shift register, flushes the transmit fifo, and sets wr7? bit 5 to 1. if the transmitter generates the in terrupt or dma request for data when the top byte of the fifo is empty (wr7? bit 5 is 0), the system allows for a long respon se time to the data request without underflowing. the interrupt service routine (isr) writes 1byte and then tests rr0 bit 2. the dma request on transmit in this mode is set to 0 after each data write (that is, tbe), rr0 bit 2, is set to 1 wh en the top byte of the fifo is empty. wr7? bit 5 resets to 1. in applications for which the interrupt frequency is important, the transmit isr can be optimized by programming the escc to generate the tbe interrupt onl y when the fifo is completely empty (wr7? bit 5 is 1) and, wr iting 4 bytes to fill the fifo. when wr7? bit 5 is 1, only one dma request is generated, filling the bottom of the fifo. however, this may be advantageous for applications wher e the possible reassertion of the dma request is not required. the tbe status b it, rr0 bit 2, is set to 1 when the top byte of the fifo is empty. wr7? bit 5 is set to1 after a hardware or channel reset. 8-byte receive fifo the escc has an 8-byte receive fifo with prog rammable interrupt leve ls. it is not neces - sary to enable the 8-byte fifo as it is always available. a hardware or channel reset clears the receive shift register and flushes the re ceive fifo. the receive character available interrupt is generated as selected by wr7? bit 3. the receive character available bit, rr0 bit 0 is set to 1 when at le ast one byte is available at the top of the fifo (independent of wr7? bit 3). a dma request on receive, if enabled, is ge nerated whenever 1 byte is available in the receive fifo independent of wr7? bit 3. if more than 1 byte is available in the fifo, the wait / request pin becomes inactive and becomes active when the fi fo is emptied.
ps005308-0609 z80230/z85230/l enhancements z80230/z85230/l product specification 23 by resetting wr7? bit 3 to 0, applications wh ich have a long latency to interrupts can gen - erate the request to read data from the fifo when one byte is ava ilable. the application can then test the receive character available bit to determine if more data is available. by setting wr7? bit 3 to 0, the escc can issue an interrupt when the receive fifo is half full (4 bytes available), allowing the frequency of interrupts to be reduced. if wr7? bit 3 is 1, the receive character availa ble interrupt is generated when there are 4 bytes available. if the isr reads 4 bytes during each routine, the frequency of interrupts is reduced. if wr7? bit 3 is 1 and receive interrupt on all characters and sp ecial conditions is enabled, the receive character available inte rrupt is generated when four characters are available. however, when a character is detect ed to have a special condition, an interrupt is generated when the character is loaded into the top four bytes of the fifo. therefore, the special condition isr must be rr1 before reading the da ta to determin e which byte has the special condition. write register 7 prime (wr7?) a new register, wr7?, has been added to the escc to enable the programming of six new features. the format of this register is listed in table 4 . table 4. write register 7 prime (wr7?) wr7? is written by first setting bit 0 of write register 15 (wr15 bit 0) to 1 and then accessing wr7. all write commands to register 7 are to wr7? while wr 15 bit 0 is set to bit 7 6 5 4 3 2 1 0 r/w w w w /w w w w w reset 0 0 0 0 0 0 0 0 note: r = read w = write x = indeterminate bit ? position r/w value description 7 w 0 reserved, must be 0 6 w extended read enable 5 w transmit fifo int level 4 w dtr / req timing mode 3 w receive fifo int level 2 w auto rts deactivation 1 w auto eom reset 0 w auto transmit flag
ps005308-0609 z80230/z85230/l enhancements z80230/z85230/l product specification 24 1. wr15 bit 0 must be reset to 0 to address th e sync character in register wr7. if bit 6 of wr7? is set to 1, then wr7? can be read by performing a read cy cle to rr14. the wr7? features remain enabled until specifically disable d or by a hardware or software reset. bit 5 is set to 1 and all other bits are reset to 0 after a reset. for applications which use either the zilo g z8x30scc or z80230, these two device types can be identified in softwa re with the following test: 1. write 01h to write register 15 2. read register 15 if bit 0 is set to 0, the device is z8x30scc. if bit 0 is set to 1, it is a z80c30. if the device is z8xc30, a write to wr15 is required before proceeding. if the device is z80230, all writes to address 7 are to wr7? until wr15 is set to 0. the wr7 register bits are described below: bit 7 (not used) this bit must always be 0. bit 6 (extended read enable) setting this bit to 1 enables wr3, wr4, wr5, wr7? and wr10 to be read by issuing a read command for rr9 (wr3) rr4, rr5, rr14 (wr7?) and rr11 (wr10), respec - tively. bit 5 (transmit fifo interrupt level) if this bit is set to 1, the tbe interrupt is generated when the transm it fifo is completely empty. if this bit is set to 0, the tbe interrupt is generated when the top byte of the trans - mit fifo is empty. this bit is set following a hardware or channel reset. in dma request on transmit mode, when using either the w / req or dtr / req pins, the request is asserted when the tx fifo is completely empty if wr7? bit 5 is set to 1. the request is asserted when the top byte of the fifo is empty if bit 5 is reset. bit 4 (dtr /req timing) if this bit is set to 1 and the dtr / req pin is used for request mode (wr14 bit 2 is 1), the deactivation of the dtr / req pin is identical to the w / req pin as displayed in figure 12 on page 25 . if this bit is reset, th e deactivation time is 4tcpc.
ps005308-0609 z80230/z85230/l enhancements z80230/z85230/l product specification 25 figure 12. dma request on transmit deactivation timing bit 3 (receive fifo interrupt level) this bit sets the interrupt level of the receive fifo. if this bit is set to 1, the receive data available bit is asserted when the receive fifo is half full (4 bytes available). if this bit is reset to 0, the receive data available interru pt is requested when all bytes are set. for more information, see 8-byte receive fifo on page 22 . bit 2 (automatic rts pin deassertion) this bit controls the timing of the deassertion of the rts pin in sdlc mode. if this bit is 1 and wr5 bit 1 is set to 0 during the transmission of an sdlc frame, the deassertion of the rts pin is delayed until the last bit of the closing flag clears the txd pin. the rts pin is pulled high after the rising edge of the tr ansmit clock cycle from th e last bit of the clos - ing flag. this action implies that the escc must be programmed for flag on underrun (wr10 bit 2 is 0) for the rts pin to deassert at the end of the frame. this feature works independently of the progra mmed transmitter idle state. in synchronous mode other than sdlc, the rts pin immediately follows the state programmed into wr5 bit 1. when wr7? bit 2 is set to 0, the rts follows the state of wr5 bit 1. bit 1 (automatic eom reset) if this bit is 1, the escc automatically rese ts the tx underrun/eom latch and presets the transmit crc generator to its pr ogrammed preset state (per values set in wr5 bit 2 and wr10 bit 7). therefore, it is not necessary to issue the reset tx underrun/eom latch command when this feature is enabled. bit 0 (automatic tx sdlc flag) if this bit is 1, the escc automatically tran smits an sdlc flag before transmitting data. this action removes the requirement to reset th e mark idle bit (wr10 bit 3) before writing data to the transmitter. wr d7?d0 dtr /req wait /req transmit data wr7 bit 4 =1 wr7 bit 4 = 0
ps005308-0609 z80230/z85230/l enhancements z80230/z85230/l product specification 26 historically, the scc latched the databus on the falling edge of wr . however, as many cpus do not guarantee that th e databus is valid when the wr pin goes low, zilog modi - fied the databus timing to allow a maximum delay of 20 ns from the wr signal going active low to the latching of the databus. crc reception in sdlc mode in sdlc mode, the entire crc is clocked in to the receive fifo. the escc completes clocking in the crc to allow it to be retran smitted or manipulated so ftware. in the scc, when the closing flag is reco gnized, the contents of the receive shift register are immedi - ately transferred to the receiv e fifo, resulting in the loss of the last two bits of the crc. in the escc, it is not necessary to program this feature. when the closing flag is detected, the last 2 bits of the crc are transferre d into the receive fifo. in all other ? synchronous mode, the escc does not clock in the last 2 crc bits (same as the scc). txd forced high in sdlc with nrz i encoding when marking idle when the escc is programmed for sdlc mode with nrzi data encoding and mark idle (wr10 bit 6 is 0, bit 5 is 1, bit 3 is 1), the txd pin is automatically forced high when the transmitter enters the mark idle state. there are several different wa ys for the transmitter to enter the idle state. in each of the followi ng cases the txd pin is forced high when the mark idle condition is reached: ? data, crc, flag, and idle ? data, flag, and idle ? data, abort (on underrun), and idle ? data, abort (command), and idle ? idle flag and comm and to idle mark the force high feature is disabled wh en the mark idle bit is set to 0. this feature is used in combination with th e automatic sdlc opening flag transmission feature, wr7? bit 0 is 1, to assure that data packets are formatted correctly. in this case, the cpu is not required to issue any commands. if wr7? bit 0 is 0, as on the scc, the mark idle bit (wr10 bit 3), is set to 1, to enable flag transmission before an sdlc packet trans - mits. improved transmit interrupt handling the escc latches the tbe interrupt because the crc is loaded into the transmit shift register even if the tbe interrupt, due at the l ast data byte, has not been reset. the end of a
ps005308-0609 z80230/z85230/l enhancements z80230/z85230/l product specification 27 synchronous frame is guaranteed to generate two tbe interrupts even if a reset transmit buffer interrupt command for the data created interrupt is issued af ter the crc interrupt occurs (time a in figure 13 ). two reset tbe commands are required. the txip latches if the eom latch resets before the end of the frame. figure 13. txip latching dpll counter tx clock source when the dpll is selected as th e transmit clock source, the dpll counter output is the dpll source clock divided by the appropriate divisor for the programmed data encoding format. in fm mode (fm0 or fm1), the dpll counter output signal is the input frequency divided by 16. in nrzi mode, the dpll counter output signal is the input clock cycle divided by 32. this feature provides a jitter -free output signal that replaces the dpll transmit clock out - put as the transmit clock source. this action h as no effect on the use of the dpll as the receive clock source (see figure 14 ). figure 14. dpll outputs read register 0 status latched during read cycle the contents of read register 0, rr0 is latched during a read operation. the escc pre - vents the contents of rr0 from changing during a read operation. but, the scc allows the status of rr0 to change while reading th e register and may require reading rr0 twice. the contents of rr0 is updated after the rising edge of rd signal. data data crc1 crc2 flag txbe txip bit txip 1 txip 2 time a dpll clk dpll dpll output to receiver dpll counter dpll output to transmitter input frequency divided by 16 (fm0 or fm1) input clock cycle divided by 32 for nrzi input
ps005308-0609 z80230/z85230/l enhancements z80230/z85230/l product specification 28 software interrupt acknowledge the z80230/z85230/l interrupt acknowledge cycle can be initiated using software. if write register 9 (wr9 bit 5 is 1), read register 2 (rr2) results in an interrupt intack cycle, a software ack nowledgment causes the int pin to go high. the ieo pin goes low. the interrupt under service (ius) latch is set to the highest prior ity pending interrupt. when a hardware intack signal is desired, a software acknowledge cycle requires that a reset highest ius command be issued in th e isr. if rr2 is read from channel a, the unmodified vector is returned. if rr2 is read from channel b, then the vector is modified to indicate the source of the interrupt. the vector includes status (vis) and no vector (nv) bits in wr9 are ignored when wr9 bit 5 is set to 1. if the intack and iei pins are not used, they are pulled up to v cc through a resistor ? (2.2 k?, typical). fast sdlc transmit data interrupt response to facilitate the transmission of back-to-b ack sdlc frames with a single shared flag between frames, the escc allows data for a second frame to be written to the transmit fifo after the tx underrun/eom interrupt o ccurs. this feature a llows application soft - ware more time to write the data to the tran smitter while allowing the current frame to conclude with crc and flag. th e scc required that data no t be written to the transmitter until a tbe interrupt is generated after the crc completed transmission. if data is written to the transmit fifo after the transmit underrun/eom interrupt is issued but before the tbe interrupt is issued, th e automatic eom reset function is enabled (wr7? bit 1 is 1). consequently, the commands reset tx/underrun eom latch and reset tx crc generator must never be used. sdlc fifo frame status enhancement when used with a dma controller, the es cc sdlc frame status fifo enhancement maximizes the escc?s ability to receive high- speed, back-to-back sdlc messages. it minimizes frame overruns due to cpu latencies in responding to interrupts. the feature (displayed in figure 15 on page 29 ) includes: ? 10-bit deep by 19-bit wide status fifo ? 14-bit receive byte counter ? control logic the 10 x 19 bits status fifo is sepa rate from the 8-byte receive data fifo. when the enhancement is enable d, the status in read register 1 (rr1) and byte count for the sdlc frame are stored in the 10- x 19-b it status fifo. this action allows the dma
ps005308-0609 z80230/z85230/l enhancements z80230/z85230/l product specification 29 controller to transfer the next frame into memory while the cpu ve rifies the previously received frame. figure 15. sdlc frame status fifo 1. all sent bypasses mux and equals contents of scc status register. 2. parity bits bypass mux and equals contents of scc status register. 3. eof is set to 1 whenever reading from the fifo. summarizing the operation: data is received, assembled, and loaded into the 8-byte fifo before transferring to memo ry by the dma controller. interface to scc 2 bits 6 bits rr1 bit bit 6 bits 5-0 rr6 6-bit mux 5 bits eof=1 6 bits 7 fifo array 10- by 19- bits 5 bits 14 bits 8 bits rr1 scc status register residue bits (3) overrun, crc error byte counter frame status fifo circuitry reset on flag detect increment on each received character enable count in sdlc eof signal status read complete tail pointer 4-bit counter head pointer 4-bit counter 4-bit comparator over equal en fifo enable wr15 bit 2 set enables status fifo rr7 5 - 0 + rr6 7-0 14-bit byte counter (16 kb maximum count) rr7 bit 7 fifo data-available status bit (1 during read) rr7 bit 7 fifo overflow status bit (1 on overflow) see notes:, next. notes:
ps005308-0609 z80230/z85230/l enhancements z80230/z85230/l product specification 30 when a flag is received at the end of an sdlc frame, the frame by te count from the 14-bit counter and 5 status bits are lo aded into the status fifo fo r verification by the cpu. the crc checker is automatically r eset in preparation for the ne xt frame, which starts immedi - ately. because the byte count and status are saved for each frame, the message integrity can be verified at a later time. status information fo r up to ten frames is stored before a status fifo overrun occurs. if a frame is term inated with an abort command, the byte count and status is loaded to the status fifo and the counter is reset for the next frame. fifo enable/disable this fifo buffer is enabled when wr15 bit 2 is 1 and the escc is in the sdlc/hdlc mode. otherwise, the status register contents bypass the fifo and transfer directly to the bus interface (the fifo pointer logic is rese t either when disabled or by a channel or power-on reset). when the fifo mode is disabled, the escc is downward-compatible with the nmos z8030/z8530. the fifo mode is disabled on power-up (wr15 bit 2 set to 0 on reset). the effects of backward compatib ility on the register set are that rr4 is an image of rr0, rr5 is an image of rr1, rr6 is an image of rr2, and rr7 is an image of rr3. for information on the added registers, see read registers on page 53 . the status of the fifo enable signal is read at rr15 bit 2. if the fifo is enabled, the bit is set to 1; oth - erwise it is reset to 0. fifo read operation when wr15 bit 2 is 1 and the fifo is not empty, the next read status register rr1 or the additional registers rr7 and rr6, reads the fi fo. reading status regi ster rr1 causes one location of the fifo to empty, so status is read after read ing the byte count; otherwise the count is incorrect. before the fifo underflows, it is disabled . in this case, the multiplexer is switched to allow status to re ad directly from the status regi ster. in this state, reads from rr7 and rr6 are undefined bit 6 of rr7 (fifo data available) status data is coming from the fifo or directly from the status register, b ecause it is set to 1 whenever the fifo is not empty. since all status bits are not stored in the fi fo, the all sent, parity, and eof bits bypass the fifo. the status bits sent through the fifo are the three residue bits, overrun, and crc error. the correct sequence for polling the byte co unt and fifo logic is rr7, rr6, then rr1 (reading rr6 is optional). add itional logic prevents the fifo from emptying by multiple reads from rr1. the read from rr 7 latches the fifo empty/full status bit (bit 6) and steers the status multiplexer to read the escc megacell in stead of the status fifo
ps005308-0609 z80230/z85230/l enhancements z80230/z85230/l product specification 31 (because the status fifo is empty). the read fr om rr1 allows an entr y to be read from the fifo (if the fifo is empty, the logi c prevents a fifo underflow condition). fifo write operation when the end of an sdlc frame is received and the status fifo is enabled, the contents of the status and byte-count registers load in to the fifo. the eof signal increments the fifo. if the fifo overflows, the rr7 bit 7 (fifo overflow) is set, indicating the over - flow. this bit and the fifo control logic is reset by disabling and re-enabling the fifo control bit (wr15 bit 2). for details about fifo control timing during an sdlc frame, see figure 16 . figure 16. sdlc byte counting detail sdlc status fifo anti-lock feature when the frame status fifo is enabled and the escc is programmed for special receive condition only (wr1 bit 4 = bi t 3=1), the data fifo is not locked when a character with eof status is read.when eof status is at the top of the fifo, an interrupt with a vector for receive data is ge nerated. the command reset highest ius must be issued at the end of the isr regardless of whether an inte rrupt acknowledge cycle was executed (hard - ware or software). this action allows the dma to complete the transfer of the received frame to memory, then interrupt the cpu that a frame was comp leted, without lockin g the fifo. because in the receive interrupt on special cond ition only mode the interrupt vec - tor for receive data is not used , it indicates that the last byte of a frame has been read from the receive fifo. reading the frame status (crc, byte count and other status stored in the status fifo) determines that eof is not required. when a character with a spec ial receive condition other than eof is received (receiver overrun or parity), a special receive condition interrupt is generated after the character is read from the fifo and the recei ve fifo is locked until the error reset command is issued. 0123 567 4 0123 567 40 f add dc d fadd dcc d f do not load counter on first flag. reset byte counter here internal byte strobe increments counter reset byte counter, then load counter into fifo and increment ptr. internal byte strobe increments counter reset byte counter, then load counter into fifo and increment ptr f c
ps005308-0609 programming z80230/z85230/l product specification 32 programming the escc contains write registers in each ch annel that are progra mmed by the system separately to configure the function of each channel. in the z85230/l escc, the data fifos are dire ctly accessible by selecting a high on the ? d/ c pin. except wr0 and rr0, programming the write registers requires two write oper - ations and reading a read register requires a writ e and a read operation. the first write is to wr0 which contains bits that point to the sel ected register. if the next operation is a write the selected write register is written. if the ne xt operation is a read, the selected read regis - ter is read. the pointer bits are automatically cleared after the second operation so the next read or write comes from rr0 or goes to wr0. it is not necessary to write 00 to wr0 to access wr0 or rr0. for the z80230 escc, the registers are direc tly addressable. a command issued to wr0b determines how the escc decodes the address placed on the address/data bus at the beginning of a read or write cycle. in shift right mode the channel select a/ b is taken from ad0 and the state of ad5 is ignored. in shift left mode, the channel select a/ b is taken from ad5 and the state of ad0 is igno red. ad7 and ad6 are always ignored as address bits and the register address itself occupies ad4?ad1. initializing the software first issues a series of commands to initialize the b asic mode of operation. these commands are followed by other comm ands to qualify conditions within the selected mode. for example, in the as ynchronous mode, character length, clock rate, number of stop bits, and even and odd parity is set first. next, the interrupt mode is set. finally, the receiver and transmitter are enabled. write registers the escc contains 16 write registers (17 coun ting the transmit buffer) in each channel. these write registers are programmed to conf igure the function of the channel. there are two registers (wr2 and wr9) shared by the two channels, which can be accessed through either of them. wr2 contains the interrupt vector for both channels. wr9 contains the interrupt control bits and reset commands. register wr7? can be written to if wr15 bit 0 is 1. z80x20 register access the z80230 registers are addressed using the address on ad7?ad0 which are latched by the rising edge of as . the shift right/shift left bit in the channel b wr0 controls which
ps005308-0609 programming z80230/z85230/l product specification 33 bits are decoded to form the register address. this bit is placed in this register to simplify programming when the current state of the shift right/shift left bit is not known. a hardware reset forces shift left mode where the address is decoded from ? ad5?ad0. in shift right mode, the addr ess is decoded from ad4?ad0. the shift right/shift left bit is written using a comm and to make the software writing to wr0 inde - pendent of the state of the shift right/shift left bit. while in the shift left mode, the register address is placed on ad4?ad0 and the channel select bit a/ b , is decoded from ad5 . in shift right mode, the register address is again placed on ad4?a d1 but the channel select a/ b is decoded from ad0. since z80230 does not contain 16 read register s, the decoding of the read registers is not complete; this state is listed in table 4 on page 23 and table 5 by parentheses around the register name. these addresses may also be us ed to access the read registers. the z80230 contains only one wr2 and wr9; these re gisters may be written from either channel. shift left mode is used when channel a and b are programmed differently. using shift left mode allows the software to sequ ence through the registers of one channel at a time. the shift right mode is used wh en the channels are programmed the same. by incrementing the address, you can program the same data value into both channel a and channel b registers. table 5 lists details of the z80x30 register map in shift left mode. table 5. z80230 register map (shift left mode) ad5 ad4 ad3 ad2 ad1 write 80230 wr15 d2=0 80230 wr15 d2=1 80230 wr15 d2=1 wr7? d6=1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 wr08 wr1b wr2 wr3b rr0b rr1b rr2b rr3b rr0b rr1b rr2b rr3b rr08 rr1b rr2b rr3b 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 wr4b wr5b wr6b wr7b (rr0b) (rr1b) rr6b rr7b (rr0b) (rr1b) (rr2b) (rr3b) (wr4b) (wr5b) rr6b rr7b 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 wr8b wr9 wr10b wr11b rr8b (rr13b) rr10b (rr15b) rr8b (rr13b) rr10b (rr15b) rr8b (wr3b) rr10b (wr10b)
ps005308-0609 programming z80230/z85230/l product specification 34 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 wr12b wr13b wr14b wr15b rr12b rr13b rr14b rr15b rr12b rr13b rr14b rr15b rr12b rr13b (wr7?b) rr15b 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 wr0a wr1a wr2 wr3a rr0a rr1a rr2a rr3a rr0a rr1a rr2a rr3a rr0a rr1a rr2a rr3a 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 wr4a wr5a wr6a wr7a (rr0a) (rr1a) (rr2a) (rr3a) (rr0a) (rr1a) rr6a rr7a (wr4a) (wr5a) rr6a rr7a 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 wr8a wr9 wr10a wr11a rr8a (rr13a) rr10a (rr15a) rr8a (rr13a) rr10a (rr15a) rr8a (wr3a) rr10a (wr10a) 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 wr12a wr13a wr14a wr15a rr12a rr13a rr14a rr15a rr12a rr13a rr14a rr15a rr12a rr13a (wr7?a) rr15a notes: 1. the register names in ( ) are the values read out from that register location. 2. wr15 bit d2 enables status fifo function (not available on nmos). 3. wr7? bit d6 enables extend read function (only on escc). table 5. z80230 register map (shift left mode) (continued) ad5 ad4 ad3 ad2 ad1 write 80230 wr15 d2=0 80230 wr15 d2=1 80230 wr15 d2=1 wr7? d6=1
ps005308-0609 programming z80230/z85230/l product specification 35 table 6 lists details of the z80x30 re gister map in shift right mode. table 6. z80x30 register map (shift right mode) ad4 ad3 ad2 ad1 ad0 write 80230 wr15 d2=0 80230 wr15 d2=1 80230 wr15 d2=1 wr7? d6=1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 wr08 wr0a wr1b wr1a rr0b rr0a rr1b rr1a rr0b rr0a rr1b rr1a rr0b rr0a rr1b rr1a 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 wr2 wr2 wr3b wr3a rr2b rr2a rr3b rr3a rr2b rr2a rr3b rr3a rr2b rr2a rr3b rr3a 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 wr4b wr4a wr5b wr5a (rr0b) (rr0a) (rr1b) (rr1a) (rr0b) (rr0a) (rr1b) (rr1a)) (wr4b) (wr4a) (wr5b) (wr5a) 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 wr6b wr6a wr7b wr7a (rr2b) (rr2a) (rr3b) (rr3a) rr12b rr13b rr14b rr15b rr12b rr13b (wr7?b) rr15b 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 wr8b wr8a wr9 wr9 rr8b rr8a (rr13b) (rr13a) rr8b rr8a (rr13b) (rr13a) rr8b rr8a (wr3b) (wr3a) 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 wr10b wr10a wr11b wr11a rr10b rr10a (rr15b) (rr15a) rr10b rr10a (rr15b) (rr15a) rr10b rr10a (wr10b) (wr10a) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 wr12b wr12a wr13b wr13a rr12b rr12b rr13b rr13a rr12b rr12b rr13b rr13a rr12b rr12b rr13b rr13a 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 wr14b wr14a wr15b wr15a rr12b rr12b rr13b rr13a rr12b rr12b rr13b rr13a (wr7?b) (wr7?b) rr13b rr13a notes: 1. the register names in ( ) are the values read out from that register location. 2. wr15 bit d2 enables status fifo function (not available on nmos). 3. wr7? bit d6 enables extend read function (only on escc).
ps005308-0609 programming z80230/z85230/l product specification 36 bits 2?0 of wr0 select registers 0?7. with the point high command, registers 8?15 are selected. table 7 lists details of the z8530 register map. table 7. z85230/l register map a/b pnt2 pnt1 pnt0 write 85230 wr15 d2=0 85230 wr15 d2=1 85230 wr15 d2=1 wr7? d6=1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 wr0b wr1b wr2 wr3b rr0b rr1b rr2b rr3b rr0b rr1b rr2b rr3b rr0b rr1b rr2b rr3b 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 wr4b wr5b wr6b wr7a (rr0b) (rr1b) (rr2b) (rr3b) (rr0b) (rr1b) rr6b rr7b (wr4b) (wr5b) rr6b rr7b 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 wr0a wr1a wr2 wr3a rr0a rr1a rr2a rr3a rr0a rr1a rr2a rr3a rr0a rr1a rr2a rr3a 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 wr4a wr5a wr6a wr7a (rr0a) (rr1a) (rr2a) (rr3a) (rr0a) (rr1a) rr6a rr7a (wr4a) (wr5a) rr6a rr7a with point high command 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 wr8b wr9 wr10b wr11b rr8b (rr13b) rr10b (rr15b) rr8b (rr13b) rr10b (rr15b) rr8b (wr3b) rr10b (wr10b) 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 wr12b wr13b wr14b wr15b rr12b rr13b rr14b rr15b rr12b rr13b rr14b rr15b rr12b rr13b (wr7?b) rr15b 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 wr8a wr9 wr10a wr11a rr8a (rr13a) rr10a (rr15a) rr8a (rr13a) rr10a (rr15a) rr8a (wr3a) rr10a (wr10a) 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 wr12a wr13a wr14a wr15a rr12a rr13a rr14a rr15a rr12a rr13a rr14a rr15a rr12a rr13a (wr7?a) rr15a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 wr0b wr1b wr2 wr3b rr0b rr1b rr2b rr3b rr0b rr1b rr2b rr3b rr0b rr1b rr2b rr3b notes: 1. the register names in ( ) are the values read out from that register location. 2. wr15 bit d2 enables status fifo function (not available on nmos). 3. wr7? bit d6 enables extend read function (only on escc).
ps005308-0609 programming z80230/z85230/l product specification 37 table 8 through table 24 on page 53 list the format of each write register. table 8. write register 0 bit 7 6 5 4 3 2 1 0 r/w w reset 00000000 r = read w = write x = indeterminate bit position r/w value description 7, 6 w 00 01 10 11 null code reset tx crc checker reset tx crc generator reset tx underrun/eom latch 5, 4, 3 000 001 010 011 100 101 110 111 null code point high reset ext/status interrupts send abort (sdlc) enable int on next rx character reset tx int pending error reset reset highest ius 2, 1, 0 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 register 0 register 1 register 2 register 3 register 4 register 5 register 6 register 7 register 8 (with point high) register 9 (with point high) register 10 (with point high) register 11 (with point high) register 12 (with point high) register 13 (with point high) register 14 (with point high) register 15 (with point high) for the 80230, bits 1 and 0 are accessible only through channel b.
ps005308-0609 programming z80230/z85230/l product specification 38 table 9. write register 1 bit 7 6 5 4 3 2 1 0 r/w w reset 00x00x00 r = read w = write x = indeterminate bit position r/w value description 7 0 1 wait/dma request enable disabled enabled 6 0 1 wait/dma request function wait request 5 0 1 wait/dma request on receive/transmit transmit receive 4, 3 00 01 10 11 receive interrupt disable rec int on first characte r or special condition int on all rx characters or special condition rx int on special condition only 2 parity is special condition 1tx int enable 0 ext int enable
ps005308-0609 programming z80230/z85230/l product specification 39 table 10. write register 2 bit 7 6 5 4 3 2 1 0 r/w w reset x xxxxxxx r = read w = write x = indeterminate bit position r/w value description 7 v7?interrupt vector 6 v6?interrupt vector 5 v5?interrupt vector 4 v4?interrupt vector 3 v3?interrupt vector 2 v2?interrupt vector 1 v1?interrupt vector 0 v0?interrupt vector
ps005308-0609 programming z80230/z85230/l product specification 40 table 11. write register 3 bit 7 6 5 4 3 2 1 0 r/w w reset x xxxxxx0 r = read w = write x = indeterminate bit position r/w value description 7, 6 00 01 10 11 rx 5 bits/character rx 7 bits/character rx 6 bits/character rx 8 bits/character 5 auto enable 4 enter hunt mode 3 rx crc enable 2 address search mode (sdlc) 1 sync character load inhibit 0 rx enable
ps005308-0609 programming z80230/z85230/l product specification 41 table 12. write register 4 bit 7 6 5 4 3 2 1 0 r/w w reset x xxxx1x0 r = read w = write x = indeterminate bit position r/w value description 7, 6 00 01 10 11 x1 clock mode x16 clock mode z32 clock mode x64 clock mode 5, 4 00 01 10 11 8-bit sync character 16-bit sync character sdlc mode (01111110 flag) external sync mode 3, 2 00 01 10 11 sync modes enable 1 stop bit/character 1.5 stop bits/character 2 stop bits/character 1 0 1 parity even/odd odd even 0 parity enable
ps005308-0609 programming z80230/z85230/l product specification 42 table 13. write register 5 bit 7 6 5 4 3 2 1 0 r/w w reset 0 xx0000x r = read w = write x = indeterminate bit position r/w value description 7dtr 6, 5 00 01 10 11 tx 5 bits (or less)/character tx 7 bits/character tx 6 bits/character tx 8 bits/character 4 send break 3 tx enable 2 0 1 crc-16/crc-ccitt crc-ccitt crc-16 1rts 0 tx crc enable
ps005308-0609 programming z80230/z85230/l product specification 43 table 14. write register 6 bit 7 6 5 4 3 2 1 0 r/w w reset xx x x x x x x r = read w = write x = indeterminate bit position r/w value description monosync 8 bits monos ync 6 bits bisync ? 16 bits bisync ? 12 bits sdlc sdlc (address range) 7 sync7 sync1 sync7 sync3 adr7 adr7 6 sync6 sync0 sync6 sync2 adr6 adr6 5 sync5 sync5 sync5 sync1 adr5 adr5 4 sync4 sync4 sync4 sync0 adr4 adr4 3 sync3 sync3 sync3 1 adr3 x 2 sync2 sync2 sync2 1 adr2 x 1 sync1 sync1 sync1 1 adr1 x 0 sync0 sync0 sync0 1 adr0 x
ps005308-0609 programming z80230/z85230/l product specification 44 table 15. write register 7 bit 7 6 5 4 3 2 1 0 r/w w reset xxxxxxxx r = read w = write x = indeterminate bit position r/w value description this column contains no data monosync 8 bits monosync 6 bits bisync 16 bits bisync 12 bits sdlc 7 sync7 sync5 sync15 sync11 0 6 sync6 sync4 sync14 sync10 1 5 sync5 sync3 sync13 sync9 1 4 sync4 sync2 sync12 sync8 1 3 sync3 sync1 sync11 sync7 1 2 sync2 sync0 sync10 sync6 1 1 sync1 x sync9 sync5 1 0 sync0 x sync8 sync4 0
ps005308-0609 programming z80230/z85230/l product specification 45 table 16. write register 7? bit 7 6 5 4 3 2 1 0 r/w w reset 0 0100000 r = read w = write x = indeterminate bit position r/w value description 7 0 not used. must be 0. 6 extended read enable 5 tx fifo int level 4dtr /req timing mode 3 rx fifo int level 2 auto rts deactivation 1 auto eom reset 0 auto tx flag
ps005308-0609 programming z80230/z85230/l product specification 46 table 17. write register 8 bit 7 6 5 4 3 2 1 0 r/w w reset 0 0100000 r = read w = write x = indeterminate bit position r/w value description 7d7 6d6 5d5 4d4 3d3 2d2 1d1 0d0
ps005308-0609 programming z80230/z85230/l product specification 47 table 18. write register 9 bit 7 6 5 4 3 2 1 0 r/w w hardware reset 1 10000xx channel reset x x0xxxxx r = read w = write x = indeterminate bit position r/w value description 7, 6 00 01 10 11 no reset channel reset b channel reset a force hardware reset 5 software intack enable 4 0 1 status high/ status low low high 3 master interrupt enable 2 disable lower chain 1 no vector 0 vector includes status
ps005308-0609 programming z80230/z85230/l product specification 48 table 19. write register 10 bit 7 6 5 4 3 2 1 0 r/w w hardware reset 0 0000000 channel reset 0 xx00000 r = read w = write x = indeterminate bit position r/w value description 7 crc preset i/o 6, 5 00 01 10 11 nrz nrzi fm 1 (transition = 1) fm 0 (transition = 0) 4 go active on poll 3 0 1 mark/flag idle flag idle mark idle 2 0 1 abort/flag on underrun flag abort 1 loop mode 0 0 1 6-bit/8-bit sync 8-bit 6-bit
ps005308-0609 programming z80230/z85230/l product specification 49 table 20. write register 11 bit 7 6 5 4 3 2 1 0 r/w w hardware reset 0 0001000 channel reset x xxxxxxx r = read w = write x = indeterminate bit position r/w value description 7 0 1 rtxc xtal/no xtal no xtal rtxc xtal 6, 5 00 01 10 11 receive clock = rtxc pin receive clock = trxc pin receive clock = brg output receive clock = dpll output 4, 3 00 01 10 11 transmit clock = rtxc pin transmit clock = trxc pin transmit clock = brg output transmit clock = dpll output 2 0 1 trxc input/output output input 100 01 10 11 trxc out = xtal output trxc out = transmit clock trxc out = brg output trxc out = dpll output
ps005308-0609 programming z80230/z85230/l product specification 50 table 21. write register 12 bit 7 6 5 4 3 2 1 0 r/w w reset x xxxxxxx r = read w = write x = indeterminate bit position r/w value description (lower byte of time constant) 7tc7 6tc6 5tc5 4tc4 3tc3 2tc2 1tc1 0tc0
ps005308-0609 programming z80230/z85230/l product specification 51 table 22. write register 13 bit 7 6 5 4 3 2 1 0 r/w w reset x xxxxxxx r = read w = write x = indeterminate bit position r/w value description (upper byte of time constant) 7tc15 6tc14 5tc13 4tc12 3tc11 2tc10 1tc9 0tc8
ps005308-0609 programming z80230/z85230/l product specification 52 table 23. write register 14 bit 7 6 5 4 3 2 1 0 r/w w reset x xxxxxxx r = read w = write x = indeterminate bit position r/w value description (upper byte of time constant) 7, 6, 5 000 001 010 011 100 101 110 111 null command enter search mode reset missing clock disable dpll set source - brg set source = rtxc set fm mode set nrzi mode 4 local loopback 3 auto echo 2 dtr/request generator source 1 brg source 0 brg enable
ps005308-0609 programming z80230/z85230/l product specification 53 read registers the escc contains ten read registers (eleve n, counting the receive buffer rr8) in each channel. four of these may be read to ob tain status information (rr0, rr1, rr10, and rr15). two registers, rr12 and rr13, are read to learn the brg time constant. rr2 contains either the unmodified interrupt vector, channel a, or the vector modi fied by status infor - mation, channel b. rr3 contains the interrupt pe nding (ip) bits for channel a. rr6 and rr7 contain the information in the sd lc frame status fifo, but is only read when wr15 bit 2 is 1. if wr7? bit 6 is 1, write registers wr3, wr4, wr5, and wr10 can be read as rr9, rr4, rr 5, and rr14, respectively. table 25 on page 54 through table 40 on page 69 list the format of the read registers. table 24. write register 15 bit 7 6 5 4 3 2 1 0 r/w w reset 1 1110000 r = read w = write x = indeterminate bit position r/w value description 7 break/abort interrupt enable 6 tx underrun/eom interrupt enable 5cts interrupt enable 4 sync /hunt 3 dcd interrupt enable 2 sdlc fifo enable 1 zero count interrupt enable 0 wr7? sdlc feature enable
ps005308-0609 programming z80230/z85230/l product specification 54 table 25. read register 0 bit 7 6 5 4 3 2 1 0 r/w r reset x 1 xxx1 0 0 r = read w = write x = indeterminate bit position r/w value description 7 break/abort 6 tx underrun/eom 5cts 4 sync /hunt 3 dcd interrupt enable 2 tx buffer empty 1 zero count 0 rx character available
ps005308-0609 programming z80230/z85230/l product specification 55 table 26. read register 1 bit 7 6 5 4 3 2 1 0 r/w r reset 0 000011x r = read w = write x = indeterminate bit position r/w value description 7 eof (sdlc) 6 crc/framing error 5 rx overrun error 4parity error 3 residue code 0 2 residue code 1 1 residue code 2 0 all sent
ps005308-0609 programming z80230/z85230/l product specification 56 table 27. read register 2 bit 7 6 5 4 3 2 1 0 r/w r reset x xxxxxxx r = read w = write x = indeterminate bit position r/w value description (interrupt vector) 7v7 6v6 5v5 4v4 3v3 2v2 1v1 0v0 these bits include status information when read from channel b.
ps005308-0609 programming z80230/z85230/l product specification 57 table 28. read register 3 bit 7 6 5 4 3 2 1 0 r/w r reset x xxxxxxx r = read w = write x = indeterminate bit position r/w value description 70 60 5 channel a rx ip 4 channel a tx ip 3 channel a ext/status ip 2 channel b rx ip 1 channel b tx ip 0 channel b ext/status ip bits 5, 4, 3, 2, 1 and 0 are always 0 when read from channel b.
ps005308-0609 programming z80230/z85230/l product specification 58 table 29. read register 4 bit 7 6 5 4 3 2 1 0 r/w r reset x xxxxxxx r = read w = write x = indeterminate bit position r/w value description 7, 6 00 01 10 11 x1 clock mode x16 clock mode z32 clock mode x64 clock mode 5, 4 00 01 10 11 8-bit sync character 16-bit sync character sdlc mode (01111110 flag) external sync mode 3, 2 00 01 10 11 sync modes enable 1 stop bit/character 1.5 stop bits/character 2 stop bits/character 1 0 1 parity even/odd odd even 0 parity enable this register reflects the contents of rr0 if wr7? bit 6 is enabled.
ps005308-0609 programming z80230/z85230/l product specification 59 table 30. read register 5 bit 7 6 5 4 3 2 1 0 r/w r reset x xxxxxxx r = read w = write x = indeterminate bit position r/w value description 7dtr 6, 5 00 01 10 11 tx 5 bits (or less)/character tx 7 bits/character tx 6 bits/character tx 8 bits/character 4 send break 3 tx enable 2 0 1 crc-16/crc-ccitt crc-ccitt crc-16 1rts 0 tx crc enable this register reflects the contents of rr1 if wr7? bit 6 is enabled.
ps005308-0609 programming z80230/z85230/l product specification 60 table 31. read register 6 bit 7 6 5 4 3 2 1 0 r/w r reset x xxxxxxx r = read w = write x = indeterminate bit position r/w value description 7bc7 6bc6 5bc5 4bc4 3bc3 2bc2 1bc1 0bc0 this register can be accessed only if wr15 bit 2 is 1. if this bit is not enabled this register reflects rr2.
ps005308-0609 programming z80230/z85230/l product specification 61 table 32. read register 7 bit 7 6 5 4 3 2 1 0 r/w r reset x xxxxxxx r = read w = write x = indeterminate bit position r/w value description 7 0 1 fos: fifo status overflow fifo overflowed normal 6 0 1 fda: fifo data available status reads from fifo status reads from escc 5bc13 4bc12 3bc11 2bc10 1bc9 0bc8 this register can be accessed only if wr15 bit 2 is 1. if this bit is not enabled this register reflects rr3.
ps005308-0609 programming z80230/z85230/l product specification 62 table 33. read register 8 bit 7 6 5 4 3 2 1 0 r/w r reset 0 0100000 r = read w = write x = indeterminate bit position r/w value description 7d7 6d6 5d5 4d4 3d3 2d2 1d1 0d0
ps005308-0609 programming z80230/z85230/l product specification 63 table 34. read register 9 bit 7 6 5 4 3 2 1 0 r/w r hardware reset 110000xx channel reset xx0xxxxx r = read w = write x = indeterminate bit position r/w value description 7, 6 00 01 10 11 no reset channel reset b channel reset a force hardware reset 5 software intack enable 4 0 1 status high/status low low high 3 master interrupt enable 2 disable lower chain 1no vector 0 vector includes status to access this register wr7? bit 6 must be enabled.
ps005308-0609 programming z80230/z85230/l product specification 64 table 35. read register 10 bit 7 6 5 4 3 2 1 0 r/w r reset 0 0100000 r = read w = write x = indeterminate bit position r/w value description 7 one clock missing 6 two clocks missing 50 4 loop sending 30 20 1 on loop 00
ps005308-0609 programming z80230/z85230/l product specification 65 table 36. read register 11 bit 7 6 5 4 3 2 1 0 r/w r hardware reset 00000000 channel reset xxxxxxxx r = read w = write x = indeterminate bit position r/w value description 7 crc preset i/o 6, 5 00 01 10 11 nrz nrzi fm1 (transition = 1) fm0 (transition = 0) 4 go active on poll 3 0 1 mark/flag idle flag idle mark idle 2 0 1 abort flag on underrun flag abort 1 loop mode 0 0 1 6-bit/8-bit sync 8-bit sync 6-bit sync to access this register wr7? bit 6 must be enabled. if this bit is not enabled, this register reflects rr15.
ps005308-0609 programming z80230/z85230/l product specification 66 table 37. read register 12 bit 7 6 5 4 3 2 1 0 r/w r reset x xxxxxxx r = read w = write x = indeterminate bit position r/w value description (lower byte of time constant) 7tc7 6tc6 5tc5 4tc4 3tc3 2tc2 1tc1 0tc0
ps005308-0609 programming z80230/z85230/l product specification 67 table 38. read register 13 bit 7 6 5 4 3 2 1 0 r/w r reset x xxxxxxx r = read w = write x = indeterminate bit position r/w value description (upper byte of time constant) 7tc15 6tc14 5tc13 4tc12 3tc11 2tc10 1tc9 0tc8
ps005308-0609 programming z80230/z85230/l product specification 68 table 39. read register 14 bit 7 6 5 4 3 2 1 0 r/w r reset 0 0100000 r = read w = write x = indeterminate bit position r/w value description 7 0 not used. must be 0. 6 extended read enable 5 tx fifo int level 4dtr /req timing mode 3 rx fifo int level 2 auto rts deactivation 1 auto eom reset 0 auto tx flag to access this register wr7? bit 6 must be enabled. if this bit is not enabled this register reflects rr10.
ps005308-0609 programming z80230/z85230/l product specification 69 table 40. read register 15 bit 7 6 5 4 3 2 1 0 r/w r reset x xxxxxxx r = read w = write x = indeterminate bit position r/w value description 7 break/abort interrupt enable 6 tx underrun/eom interrupt enable 5cts interrupt enable 4 sync /hunt 3 dcd interrupt enable 2 sdlc fifo enable 1 zero count interrupt enable 0 wr7? sdlc feature enable
ps005308-0609 z80230 interface timing z80230/z85230/l product specification 70 z80230 interface timing z80230 write cycle timing the z-bus compatible escc is suited for syst em applications with multiplexed address/ data buses. two control signals, as and ds , are used by the z80230 to control bus transactions. addi - tionally, four other control signals ( cs0 , cs1, rw , and intack ) control the type of bus transaction that occurs. a bu s transaction is initiated by as . the rising edge latches the register address on the addre ss/data bus and the state of intack and cs0 . in addition to bus transactions , the interrupt section uses the as to set interrupt pending (ip) bits. therefore, as must be kept cycling for th e interrupt section to function. the z80230 generates internal control signal s in response to a register access. because as and ds have no defined phase relationship wi th pclk, the circuitry generating these internal control signals provide time for met astable conditions to disappear. this action results in a recovery time related to pclk. this recovery time app lies only to transactions involvin g the z80230, and any intervening transactions are ignored. this recovery time is four pclk cycles, measured from the fall - ing edge of ds for one access to the escc, to the falling edge of ds for a subsequent access. figure 17 displays the write cycle timing. figure 17. z80230 write cycle timing as cs0 intack a7?a0 r/w cs1 ds address data valid
ps005308-0609 z80230 interface timing z80230/z85230/l product specification 71 z80230 read cycle timing the read cycle timing for the z80230 is displayed in figure 18 . the register address on a7-a0, as well as the state of cs0 and intack , are latched by the rising edge of as . ? r/ w must be high before ds falls to indicate a read cycle. the z80230 data bus drivers are enabled while cs1 is high and ds is low. figure 18. z80230 read cycle timing z80230 interrupt ack nowledge cycle timing the interrupt acknowledge cycle timing for the z80230 is displayed in figure 19 on page 72 . the address on a7-a0 and the state of cs0 and intack are latched by the rising - edge of as . however, if intack is low. the address on a7-a0, cs0 , cs1, and r/ w are ignored for the duration of the interrupt acknowledge cycle. the z80230 samples the state of intack on the rising edge of as , and ac parameters. parameters 7 and 8 of table 45 on page 83 , specify the setup and hold time requirements. between the rising edge of as and the falling edge of ds , the internal and external daisy chains settle, as specified in parameter 29. a system with no external daisy chain provides the time priority internal to the escc. systems using an external daisy chain must refer to note 5 of table 45 , for the time required to settle the daisy chain. if there is an interrupt pending in the escc, and iei is high when ds falls, the acknowl - edge cycle is intended for the escc. consequently, the z8 0230 sets the interrupt under service (ius) latch for the high est priority pending interrupt , and places an interrupt vec - as cs0 intack a7?a0 r/w cs1 ds address data valid
ps005308-0609 z80230 interface timing z80230/z85230/l product specification 72 tor on a7-a0. wr9 bit 1 is set to 1 to disable the placing of a vector on a bus. the int pin also goes inactive in response to the falling edge of ds . there is only one ds per interrupt acknowledge cycle. ip bits in the z80230 are updated by as , which can delay interrupt requests if the proces - sor does not supply as strobes during the time in between accesses of the z80230. figure 19. z80230 interrupt acknowledge cycle timing z85230/l timing the escc generates internal control signals from wr and rd that relate to pclk. because pclk had no defined phase relationship with wr and rd , the circuitry generat - ing the internal control signal s provides time for metastable conditions to disappear. this causes a recovery time related to pclk. the recovery time applies only to bus transac - tions involving the escc. the re covery time required for proper operation is specified as cs0 a7?a0 ds intack iei ieo int vector
ps005308-0609 z80230 interface timing z80230/z85230/l product specification 73 from the falling edge of wr or rd in the first transaction in volving the escc, to the fall - ing edge of wr or rd in the second transaction. this time must be at least four pclks regardless of which register or channel is accessed. z85230/l read cycle timing figure 20 displays read cycle timing. addresses on a/ b and d/ c and the status on intack must remain stable through out the cycle. the effective rd time reduces if ce falls after rd falls, or if it rises before rd rises. figure 20. read cycle timing (z85230/l) z85230/l write cycle timing figure 21 on page 74 displays write cycle timing. addresses on a/ b and d/ c and the sta - tus on intack must remain stable througho ut the cycle. the effective wr time reduces if ce falls after wr falls, or if it rises before wr rises. in write cycle timing, the wr sig - nal returns a high slightly be fore the address goes invalid. because many popular cpus do not guarantee that the databus is valid when wr is low, the escc no longer requires a valid databus when the wr pin is low. for more informa - tion, see ac characteristics parameter 29 available in table 47 on page 90 . a/b , d/c address valid intack ce d7?d0 data valid rd
ps005308-0609 z80230 interface timing z80230/z85230/l product specification 74 figure 21. write cycle timing (z85230/l) z85230/l interrupt ackn owledge cycle timing figure 22 displays interrupt acknowledge cycle timing. between the time intack goes low and the falling edge of rd , the internal and external iei/ieo daisy chains settle. if there is an interrupt pending in the escc and iei is high when rd falls, the acknowl - edge cycle is intended for the escc. in this case, th e escc may be programmed to respond to rd low by placing its interrupt v ector on d7?d0. it then sets the appropriate ius latch internally. if the external daisy ch ain is not used, then ac parameter 38 is required to settle the interrupt priority dais y chain internal to th e escc. if the external daisy chain is used, follow the equa tion in ac characteristics note 5 ( table 47 on page 90 ) to calculate the required daisy chain settle time. figure 22. interrupt acknowledge cycle timing (z85230/l) a/b , d/c address valid intack ce d7?d0 address valid wr vector intack rd d7?d0
ps005308-0609 electrical characteristics z80230/z85230/l product specification 75 electrical characteristics absolute maximum ratings stresses greater than those listed in this secti on can cause permanent damage to the device. these ratings are stress ratings only. operatio n of the device at any condition above those indicated in the operational sec tion of this specification is not implied. exposure to abso - lute maximum rating conditions for exte nded periods can affect reliability. standard test conditions the dc characteristics and capacitance sections apply for the following standard test ? conditions, unless otherwise no ted. all voltages reference gnd. positive current flows into the referenced pin. stan dard conditions are as follows: ? gnd = 0 v ? t ? as specified in ordering information ? +4.5v ?? v cc ?? +5.5v" or +3.0 v ? v cc ?? +3.6v (z8523l only) v cc supply voltage range ?0.3 v to +7.0 v voltages on all pins with respect to gnd ?0.3 v to v cc +0.3 v operating ambient temperature see ordering information on page 107 storage temperatures ?65o c to +150o c
ps005308-0609 electrical characteristics z80230/z85230/l product specification 76 figure 23 displays typical test load configurations. figure 23. standard and open-drain test loads capacitance table 41 lists the capacitance parameters and cont ains the symbols and test conditions for each. miscellaneous gate count?11,000 for both z80230 and z85230/l. table 41. capacitance parameters symbol parameter min max unit test condition c in input capacitance 10 pf unmeasured pins returned to ground c out output capacitance 15 pf c i/o bidirectional capacitance 20 pf note: f = 1 mhz, over specified temperature range. from output under test 100pf 250a 2.1k +v cc standard test load +v cc 2.2k from output 50pf open-drain test load
ps005308-0609 electrical characteristics z80230/z85230/l product specification 77 dc characteristics table 42 lists the dc characteristic s for the z80230/z85230 device. table 42. z80230/z85230 dc characteristics symbol parameter min. typ. max. unit condition v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage ? 0.3 0.8 v v oh1 output high voltage 2.4 v ioh = ? 1.6 ma v oh2 output high voltage v cc ? 0.8 v ioh = ? 250 ? a v ol output low voltage 0.4 v iol = +2.0 ma i il input leakage 10.0 a 0.4 ps005308-0609 electrical characteristics z80230/z85230/l product specification 78 table 43 lists the dc characteris tics for the z8523l device. ac characteristics figure 24 on page 79 displays the z80230 read/write timing diagram. table 43. z8523l dc characteristics symbol parameter min. typ. max. unit condition v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage ? 0.3 0.2*v cc v v oh1 output high voltage 2.4 v ioh = ? 1.6 ma v oh2 output high voltage v cc ? 0.4 v ioh = ? 250 ? a v ol output low voltage 0.2 v iol = +2.0 ma i il input leakage 10.0 a 0.4 ps005308-0609 electrical characteristics z80230/z85230/l product specification 79 figure 24. z80230 read/write timing diagram 1 2 3 4 5 6 14 7 8 9 10 11 12 10 13 18 15 15 16 16 17 19 20 21 23 22 24 25 26 27 43 44 42 41 40 28 as cs0 cs1 intack r/w read w /r write ds ad7-ad0 write ad7-ad0 read w /req request dtr /req request int pclk w /req wait
ps005308-0609 electrical characteristics z80230/z85230/l product specification 80 figure 25 displays the z80230 interrupt acknowledge timing diagram figure 25. z80230 interrupt acknowledge timing diagram figure 26 displays the z80230 reset timing diagram figure 26. z80230 reset timing diagram table 45 lists the ac characteristics of the z80230 and table 47 lists the ac characteris - tics of z85230/l. 7 8 29 30 19 20 active valid 32 31 22 33 34 35 36 as intack ds ad7-ad0 ieo int iei as ds 35 37 38
ps005308-0609 electrical characteristics z80230/z85230/l product specification 81 figure 27 displays the z80230 general timing diagram. figure 27. z80230 general timing diagram 22 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 17 22 21 21 20 19 18 pclk w /req request w /req wait cts /trxc , rtxc receive rxd sync external cts /trxc , rtxc transmit txd cts /trxc output rtxc cts /trxc cts /trxc , dcd sync input
ps005308-0609 electrical characteristics z80230/z85230/l product specification 82 table 44 lists the z80230 general timing characteristics details. table 44. z80230 general timing characteristics no. symbol parameter 10 mhz 16 mhz notes min. max. min. max. 1 tdpc (req) pclk low to w /req valid 200 110 9 2 tspc (w) pclk low to wait inactive 300 180 9 3 tsrxc (pc) rxc high to pclk high setup time na na 1, 4, 9 4 tsrxd (rxcr) rxd to rxc high setup time 0 0 1,9 5 thrxd (rxcr) rxd to rxc high hold time 125 60 1,9 6 tsrxd (rxcf) rxd to rxc low setup time 0 0 1, 5, 9 7 thrxd (rxcf) rxd to rxc low hold time 125 60 1, 5, 9 8 tssy (rxc) sync to rxc high setup time -150 -100 1, 9 9 thsy (rxc) sync to rxc high hold time 5 5 1, 10 10 tstxc (pc) txc low to pclk high setup time na na 2, 4, 9 11 tdtxcf (txd) txc low to txd delay 150 85 2, 9 12 tdtxcr (txd) txc high to txd delay 150 85 2, 5, 9 13 tdtxd (trx) txd to trxc delay 140 80 9 14 twrtxh rtxc high width 120 80 6, 9 15 twrtxi trxc low width 120 80 6, 9 16a tcrtx rtxc cycle time 400 244 6, 7, 9 16b txrx (dpll) dpll cycle time minimum 50 31 7, 8, 9 17 tcrtxx crystal oscillator period 100 1000 100 1000 3, 9 18 twtrxh trxc high width 120 80 6, 9 19 twtrxi trxc low width 120 80 6, 9 20 tctrx trxc cycle time 400 244 6, 7, 9 21 twext dcd or cts pulse width 120 70 9 22 twsy sync pulse width 120 70 9
ps005308-0609 electrical characteristics z80230/z85230/l product specification 83 table 45 lists the z80230 read and write ac characteristics. notes: 1. rxc is rtxc or trxc , whichever is supplying the receive clock. 2. txc is trxc or rtxc , whichever is supplying the transmit clock. 3. both rtxc and sync have 30 pf capacitors to ground connected to them. 4. synchronization of rxc to pclk is eliminated in divide by four operation. 5. parameter applies only to fm encoding/decoding. 6. parameter applies only for transmitter and receiver; dpll and brg timing requirements are identical to pclk requirements. 7. the maximum transmit or receive data rate is 1/4 pclk. 8. applies to the dpll clock source only. maximum data ra te of 1/4 pclk still applie s. dpll clock must have a 50% duty cycle. 9. units in ns. 10. units in tcpc. table 45. z80230 ac characteristics no symbol parameter 10 mhz 16 mhz notes min. max. min. max 1twas as low width 30 20 8 2 tdds (as) ds rise to as fall delay 10 10 1, 8 3 tscs0 (as) cs0 to as rise setup time 0 0 1, 8 4 thcs0 (as) cs0 to as rise hold time 20 15 1, 8 5 tscs1 (ds) cs1 to ds fall setup time 50 35 1, 8 6 thcs1 (ds) cs1 to ds rise hold time 20 10 1, 8 7 tsia (as) intack to as rise setup time 10 10 8 8 thia (as) intack to as rise hold time 125 100 8 9 tsrwr (ds) r/w (read) to ds fall setup time 50 35 8 10 thrw (ds) r/w to ds rise hold time 0 0 8 11 tsrww (ds) r/w (write) to ds fall setup time 008 12 tdas (ds) as rise to ds fall delay 20 15 8 table 44. z80230 general timing characteristics (continued) no. symbol parameter 10 mhz 16 mhz notes min. max. min. max.
ps005308-0609 electrical characteristics z80230/z85230/l product specification 84 13 twdsi ds low width 125 80 8 14 trc valid access recovery time 4 4 2, 9 15 tsa (as) address to as rise setup time 10 10 1, 8 16 tha (as) address to as rise hold time 20 10 1, 8 17 tsdw (ds) write data to ds fall setup time 10 10 8 18 thdw (ds) write data to ds rise hold time 0 0 8 19 tdds (da) ds fall to data active delay 0 0 8 20 tddsr (dr) ds rise to read data not valid delay 008 21 tddsf (dr) ds fall to da ta active delay 120 70 8 22 tdas (dr) as rise to read data valid delay 190 110 8 23 tdds (drz) ds rise to read data float delay 35 20 3, 8 24 tda (dr) address required valid to read data valid delay 210 100 25 tdds (w) ds fall to wait valid delay 160 60 4, 8 26 tddsf (req) ds fall to w /req not valid delay 160 60 8 27 tddsr (req) ds fall to dtr /req not valid delay 449 28 tdas (int) as rise to int valid delay 500 175 29 tdas (dsa) as rise to ds fall (acknowledge) hold time 225 50 5 30 tsdsa ds (acknowledge) low width 125 75 8 31 tddsa (dr) ds fall (acknowledge) to read data valid delay 120 70 8 32 tsiei (dsa) iei to ds fall (acknowledge) setup time 80 50 8 33 thiei (dsa) iei to ds rise (acknowledge) hold time 008 table 45. z80230 ac characteristics (continued) no symbol parameter 10 mhz 16 mhz notes min. max. min. max
ps005308-0609 electrical characteristics z80230/z85230/l product specification 85 34 tdiei (ieo) iei to ieo delay 90 45 8 35 tdas (ieo) as rise to ieo delay 175 80 6 36 tddsa (int) ds fall (acknowledge) to int inactive delay 450 200 4, 8 37 tdds (asq) ds rise to as fall delay for no reset 15 10 8 38 tdasq (ds) as rise to ds fall delay for no reset 15 10 8 39 twres as and ds coincident low for reset7 100 75 8 40 twpcl pclk low width 40 100 26 1000 8 41 twpch pclk high width 40 1000 26 1000 8 42 tcpc pclk cycle time 100 2000 61 2000 8 43 trpc pclk rise time 10 5 8 44 tfpc pclk fall time 10 5 8 notes: 1. parameter does not apply to interrupt acknowledge transactions. 2. parameter applies only between transactions involving the escc. 3. float delay is defined as the time required for a 0.5 v change in the output with a maximum dc load and a min- imum ac load. 4. open-drain output, measured with open-drain test load. 5. parameter is system-dependent. for any zilog escc in the daisy chain. tdas (dsa) must be greater than the sum of tdas (ieo) for the highest priority device in the daisy chain. tsiei (dsa) for the zilog escc, and tdiei (ieo) for each device separati ng them in the daisy chain. 6. parameter applies only to a zilog escc pulling int low at the beginning of the interrupt acknowledge transac- tion. 7. internal circuitry allows for the reset provided by the z8 ? to be recognized as a reset by the z-escc. all timing references assume 2.0 v for a 1 and 0.8 v for a logic 0. 8. units in ns. 9. units intcpc table 45. z80230 ac characteristics (continued) no symbol parameter 10 mhz 16 mhz notes min. max. min. max
ps005308-0609 electrical characteristics z80230/z85230/l product specification 86 figure 28 displays the z80230 system timing diagram. figure 28. z80230 system timing diagram 1 2 3 4 5 6 7 8 9 10 rtxc ,trxc receive w /req request w /req wait sync output int trxc ,rtxc transmit w /req request w /req wait dtr /req request int cts ,dcd sync input int
ps005308-0609 electrical characteristics z80230/z85230/l product specification 87 table 46 lists the z80230 system timing parameter details. z85230/l ac characteristics figure 29 on page 88 displays the z85230/l read and write timing diagram. figure 30 on page 89 displays the z85230/l reset timing diagram. figure 31 on page 89 displays the z85230/l interrupt ackn owledge timing diagram. figure 32 on page 89 displays the z85230/l cycle timing diagram. table 46. z80230 system timing table no. symbol parameter 10 mhz 16 mhz notes min. max. min. max. 1 tdrxc (req) rxc high to w / req valid 13 17 13 17 2, 5 2 tdrxc (w) rxc high to wait inactive 13 19 13 19 1, 2, 5 3 tdrxc (sy) rxc high to sync valid 9 12 9 12 2, 5 4 tdrxc (int), z80230 rxc high to int valid 13 ? 2 17 ? 3 13 ? 2 17 ? 3 1, 2, 4 5 tdtxc (req) txc low to w / req valid 11 14 11 14 3, 5 6 tdtxc (w) txc low to wait inactive 8 14 8 14 1, 3, 5 7 tdtxc (drq) txc low to dtr / req valid 3, 5 8 tdtxc (int), z80230 txc low to int valid 7 ? 2 9 ? 3 7 ? 2 9 ? 3 1, 3, 4 9 tdsy (int) sync to int valid 2 ? +2 6 ? +3 2 ? +2 6 ? +3 1, 5 10 tdext (int), z80230 dcd or cts to int valid 2 3 3 8 1, 4 notes: 1. open-drain output, measured with open-drain test load. 2. rxc is rtxc or trxc, whichever is supplying the receive clock. 3. txc is trxc or rtxc , whichever is supplying the transmit clock. 4. units equal to as . 5. units equal to tcpc.
ps005308-0609 electrical characteristics z80230/z85230/l product specification 88 figure 29. z85230/l read/write timing diagram 1 2 3 4 5 6 7 8 9 10 11 12 10 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 31 29 32 33 35 34 36 37 int dtr /req request w /req request w /req wait d7?d0 write wr d7?d0 read rd ce intack a/b , d/c pclk active valid
ps005308-0609 electrical characteristics z80230/z85230/l product specification 89 figure 30. z85230/l reset timing diagram figure 31. z85230/l interrupt acknowledge timing diagram figure 32. z85230/l cycle timing diagram 46 47 48 wr rd 10 15 14 10 38 39 23 41 40 26 42 43 44 45 24 pclk intack rd d 7?d0 iei ieo int active valid 49 ce rd or wr
ps005308-0609 electrical characteristics z80230/z85230/l product specification 90 table 47 lists the z85230/l read and write ac characteristics details. table 47. z85230/l ac characteristics (20mhz applies only to z85230) no symbol parameter 8.5 mhz 10 mhz 16 mhz 20 mhz notes min max min max min max min max 1 twpcl pclk low width 45 1000 40 1000 26 1000 22 1000 6 2 txpch pclk high width 45 1000 40 1000 26 1000 22 1000 6 3 tfpc pclk fall time 10 10 5 5 6 4 trpc pclk rise time 10 10 5 5 6 5 tcpc pclk cycle time 118 2000 100 2000 61 2000 50 2000 6 6 tsa address to wr fall setup time 66 50 35 30 6 7 tha (wr) address to wr rise hold time 0 0 0 0 6 8 tsa (rd) address to rd fall setup time 66 50 35 30 6 9 tha (rd) address to rd rise hold time 0 0 0 0 6 10 tsia (pc) in ta ck to pclk rise setup time 20 20 15 15 6 11 tsiai (wr) in ta ck to wr fall setup time 140 130 70 65 1, 6 12 thia (wr) in ta ck to wr rise hold time 0 0 0 0 6 13 tsiai (rd) in ta ck to rd fall setup time 140 130 70 65 1, 6 14 thia (rd) in ta ck to rd rise hold time 0 0 0 0 6 15 thia (pc) in ta ck to pclk rise hold time 38 30 15 15 6 16 tscei (wr) ce low to wr fall setup time 0 0 0 0 6 17 thce (wr) ce to wr rise hold time 0 0 0 0 6
ps005308-0609 electrical characteristics z80230/z85230/l product specification 91 18 tsceh (wr) ce high to wr fall setup time 58 58 38 25 6 19 tscei (rd) ce low to rd fall setup time 0 0 0 0 1, 6 20 thce ((rd) ce to rd rise hold time 0 0 0 0 1, 6 21 tsceh (rd) ce high to rd fall setup time 58 50 30 25 1, 6 22 twrdi rd low width 145 125 70 65 1, 6 23 tdrd (dra) rd fall to read data active delay 0 0 0 0 6 24 tdrdr (dr) rd rise to data not valid delay 0 0 0 0 6 25 tdrdi rd fall to read data valid delay 135 120 70 65 6 26 tdrd (drz) rd rise to read data float delay 38 35 30 30 6 27 tda (dr) addr to read data valid delay 210 180 100 90 6 28 twwri wr low width 145 125 75 65 6 29 tdwr (dw) wr fall to write data valid delay 20 20 20 20 6 30 thdw (wr) write data to wr rise hold time 0 0 0 0 6 31 tdwr (w) wr fall to wait valid delay 168 100 50 50 3, 6 32 tdrd (w) rd fall to wait valid delay 168 100 50 50 3, 6 33 tdwrf (req) wr fall to w / req not valid delay 168 100 50 60 50 6 8 34 tdrdf (req) rd fall to wr / req not valid delay 168 100 50 60 50 5,6 8 table 47. z85230/l ac characteristics (20mhz applies only to z85230) (continued) no symbol parameter 8.5 mhz 10 mhz 16 mhz 20 mhz notes min max min max min max min max
ps005308-0609 electrical characteristics z80230/z85230/l product specification 92 35a tdwrr (req) wr fall to dtr / req not valid 4 4 4 4 7 35b tdwrr (req) wr fall to dtr / req not valid 168 100 50 60 50 5, 6 8 36 tdrdr (req) rd rise to dtr / req not valid delay na na na na 6 37 tdpc (int) pclk fall to int valid delay 500 320 175 160 6 38 tdiai (rd) intack to rd fall (ack) delay 145 90 50 45 4, 6 39 twrda rd (acknowledge) width 145 125 75 65 6 40 tdrda (dr) rd fall (ack) to read data valid delay 135 120 70 60 6 41 tsiei (rda) iei to rd fall (ack) setup time 95 95 50 60 45 6 8 42 thiei (rda) iei to rd rise (ack) hold time 0 0 0 0 6 43 tdiei (ieo) iei to ieo delay time 95 90 45 40 6 44 tdpc (ieo) pclk rise to ieo delay 195 175 80 80 6 45 tdrda (int) rd fall to int inactive delay 480 320 200 180 3, 6 46 tdrd (wrq) rd rise to wr fall delay for no reset 15 15 10 10 6 47 tdwrq (rd) wr rise to rd fall delay for no reset 6 15 15 10 10 6 48 twres wr and rd low for reset 145 100 75 65 6 table 47. z85230/l ac characteristics (20mhz applies only to z85230) (continued) no symbol parameter 8.5 mhz 10 mhz 16 mhz 20 mhz notes min max min max min max min max
ps005308-0609 electrical characteristics z80230/z85230/l product specification 93 49 trc valid access recovery time 4 4 4 4 2, 7 notes: 1. parameter does not apply to interrupt acknowledge transactions. 2. parameter applies only between transactions involving the escc. 3. open-drain output, measured with open-drain test load. 4. parameter is system-dependent. for any escc in the daisy chain, tdiai (rd) must be greater than the sum of tdpc (ieo) for the highest priority device in the daisy chain. tsiei (rda) for the escc and tdiei (ieo) for each device separating them in the daisy chain. 5. parameter applies to enhanced request mode only (wr7? bit 4=1) 6. units in ns. 7. units in tcpc. 8. applies to 8523l (3v version) only table 47. z85230/l ac characteristics (20mhz applies only to z85230) (continued) no symbol parameter 8.5 mhz 10 mhz 16 mhz 20 mhz notes min max min max min max min max
ps005308-0609 electrical characteristics z80230/z85230/l product specification 94 figure 33 displays the z85230/l general timing diagram figure 33. z85230/l general timing diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 21 22 22 sync input cts ,dcd trxc rtxc trxc output txd trxc ,rtxc transmit sync external rxd rtxc ,trxc receive w /req wait w /req request pclk
ps005308-0609 electrical characteristics z80230/z85230/l product specification 95 table 48 lists the z85230/l general timing characteristics details. table 49 on page 98 lists the z85230/l read/write timing characteristics details. table 48. z85230/l general timing table (20mhz applies only to z85230) no symbol parameter 8.5 mhz 10 mhz 16 mhz 20 mhz min max min max min max min max notes 1 tdpc (req) pclk to w /req valid 250 200 80 70 9 2 tdpc (w) pclk to wait inactive 350 300 180 170 9 3 tsrxc (pc) rxc to pclk setup time na na na na 1, 4, 9 4 tsrxd (rxcr) rxd to rxc setup time 00001, 9 5thrxd (rxcr) rxd to rxc hold time 150 125 50 45 1, 9 6 tsrxd (rxcf) rxd to rxc setup time 00001, 5, 9 7thrxd (rxcf) rxd to rxc hold time 150 125 50 45 1, 5, 9 8 tssy (rxc) sync to rxc setup time ?200 ?150 ?100 ?90 1, 9 9 thsy (rxc) sync to rxc hold time 55551, 10 10 tstxc (pc) txc to pclk setup time 2,4 na na na na 11 tdtxcf (txd) txc to txd delay 190 150 80 70 2, 9 12 tdtxcr (txd) txc to txd delay 190 150 80 70 2, 5, 9 13 tdtxd (trx) txd to trxc delay 200 140 80 70 9 14 twrtxh rtxc high width 130 120 80 70 6, 9 15 twrtxi rtxc low width 130 120 80 70 6, 9
ps005308-0609 electrical characteristics z80230/z85230/l product specification 96 16a tcrtx rtxc cycle time 472 400 244 200 6, 7, 9 16b txrx (dpll) dpll cycle time min. 50 50 31 31 7, 8, 9 17 tcrtxx crystal osc. period 125 1000 100 1000 61 1000 61 1000 3, 9 18 twrtxh trxc high width 130 120 80 70 5, 9 19 twtrxi trxc low width 130 120 80 70 6, 9 20 tctrx trxc cycle time 472 400 244 200 6, 7, 9 21 twext dcd or cts pulse width 200 120 70 60 9 22 twsy sync pulse width 200 120 70 60 9 notes: 1. rxc is rtxc or trxc, whichever is supplying the receive clock. 2. txc is trxc or rtxc, whichever is supplying the transmit clock. 3. both rtxc and sync have 30 pf capacitors to ground connected to them. 4. synchronization of rxc to pclk is eliminated in divide by four operation. 5. parameter applies only to fm encoding/decoding. 6. parameter applies only for transmitter and receiver; dpll and brg timing requirements are identical to case pclk requirements. 7. the maximum receive or transmit data rate is 1/4 pclk. 8. applies to the dpll clock source only. maximum data ra te of 1/4 pclk still applie s. dpll clock must have a 50% duty cycle. 9. units in ns. 10. units in tcpc. table 48. z85230/l general timing table (20m hz applies only to z85230) (continued) no symbol parameter 8.5 mhz 10 mhz 16 mhz 20 mhz min max min max min max min max notes
ps005308-0609 electrical characteristics z80230/z85230/l product specification 97 figure 34 displays the z85230/l system timing diagram. table 49 on page 98 lists the z85230/l system timing characteristics. figure 34. z85230/l system timing diagram rtxc ,trxc receive w /req request w /req wait sync output int rtxc ,trxc transmit w /req request w /req wait dtr /req request int cts ,dcd sync input int 1 2 3 4 5 6 7 8 9 10
ps005308-0609 electrical characteristics z80230/z85230/l product specification 98 table 49. z85230/l system timing characteristics (20mhz applies only to z85230) no symbol parameter 8.5 mhz 10 mhz 16 mhz 20 mhz minmaxminmaxminmaxminmaxnotes 1tdrxc (req) rxc to w /req valid 13 17 13 17 13 17 13 18 2, 4 2 tdrxc (w) rxc to wait inactive 13 17 13 17 13 17 13 18 1, 2, 4 3 tdrxc (sy) rxc to sync valid 2 47 47 47 48 2, 4 4 tdrxc (int) rxc to int valid 15 21 15 21 15 21 15 22 1, 2, 4 5tdtxc (req) txc to w /req valid 8 13 8 13 8 13 8 12 3, 4 6 tdtxc (w) txc to wait inactive 8 14 8 14 8 14 8 15 1, 3, 4 7tdtxc (drq) txc to dtr /req valid 7 10 7 10 7 10 7 11 3, 4 8 tdtxc (int) txc to int valid 7 13 7 13 7 13 7 14 1, 3, 4 9 tssy (int) sync to int valid27 27 27 27 1, 4 10 tdext (int) dcd or cts to int valid 38 38 38 39 1, 4 notes: 1. open-drain output, measured with open-drain test load. 2. rxc is rtxc or trxc , whichever is supplying the receive clock. 3. txc is trxc or rtxc , whichever is supplying the transmit clock. 4. units in tcpc.
ps005308-0609 z80230/z85230/l errata z80230/z85230/l product specification 99 z80230/z85230/l errata the current revision of zilog?s escc has si x known bugs. this sec tion identifies these bugs and provides workarounds. ius problem description the ius problem occurs unde r the following conditions: ? sdlc 10x19 status fifo is enabled ? interrupts on receive special conditions only this mode is intended for an application where received characters are read by a dma controller. eof is treated differently from ot her special conditions (for example, parity error, overrun error, and crc error). when eof is detected, the following conditions occur: ? a receive character available (rca) interrupt is generated, rather than the special conditions interrupt, as in other operating modes. ? the data fifo is not locked, as in other operating modes, and is known as the anti- lock feature. this feature allows the processor to service the eof interrupt with more latency. immedi - ate attention from the processor is not nece ssary because the data fifo is not locked. incoming data can still be deliver ed to the receive fi fo and not get lost. it also allows for operation with no servicing of the interrupt. when the eof interrupt (rca interrupt) is serviced, the processor must use the reset highest ius command to clear the eof. if an eof interrupt occurs when another lower priority interru pt is enabled (for example, ext/status interrupt is serviced) the reset highest ius command issued by the lower priority isr (to clear out the pending inte rrupt) can accidentally clear the pending eof interrupt. the reset highest ius command clears the ip bit related to the eof (in this mode, the rca ip bit) regardless of the priorities of the pending interrupts. this action causes errors under the following circumstances: ? another escc interrupt is being serviced (for example, an ext/status interrupt for transmitter underrun in full duplex operation) ? the dma reads a byte marked with eof. the corresponding ip bit is set to 1 and the int line goes low (highest priority interrupt in the daisy chain).
ps005308-0609 z80230/z85230/l errata z80230/z85230/l product specification 100 ? the processor does not acknowledge this interrupt because it is servicing another interrupt. ? the processor finishes servicing the other interrupt and uses the reset highest ius command. ? the ip bit reset corresponding to the eof, and the eof interrupt is lost. ius problem solutions the following methods can be used to work around the previously described problems. ? alternate operating mode?a similar operatin g mode can be used to achieve the same functionality with minimum code modificatio ns. the escc must operate in receive interrupts on first character and special co ndition, instead of receive interrupt on special condition only. in this mode, the anti-lock fe ature is not enabled. the fifo is locked after the last character of a frame has been transfe rred, and the interrupt condition does not disappear until after an error reset command is issued to the escc. no reset highest ius command can clear any ip bit. ? daisy chain? this workaround us es the following two conditions: ? the eof interrupt is the highest priority interrupt if only on e channel is used. ? channel a is the only ch annel issuing interrupts. if both conditions are satisfied, allowing nested interrupts ca n solve the problem. the processor servicing an interrupt on th e daisy chain must be interruptible again from another interrupt of higher priority on that same daisy chain. ? rr7 register?this workaround is applicable if the eof interrupt is used only to notify another part of the software that there has been another frame received: ? read rr7 after issuing the reset ius command. ? check bit 6 of rr7. this bit, when set, indicates that the sdlc frame fifo con- tains a valid frame. although one interrupt might have been lost (ip reset) by the reset ius command, bit 6 of rr7 always indi cates that at least one frame is available in the frame fifo. if bit 6 of rr7 is 1, notify the concerned part of the software that at least one frame is available in the frame fifo. when the sdlc fifo is enabled and receive interrupts on special conditions only is selected, software checks that there is a r eceive character available interrupt, which is generated by dma reading an eof character, and before issuing the reset highest ius command. otherwise, the eof interrupt conditions are cleared by that command.
ps005308-0609 z80230/z85230/l errata z80230/z85230/l product specification 101 figure 35 displays the procedure for resetting highest ius. figure 35. resetting highest ius from lower priority rts problem description the escc (z80230/z85230/l) contains a functional problem in automatic rts deacti - vation (see figure 36 on page 102 ). this mode is intended for sdlc applications where the rts signal from the escc is used to enable a line driver in mu lti-drop line communications. before the frame transmission, rts is asserted by an activate rts command (er5 bit1 equals 0). after the last data bit of a frame is sent, a transmit underrun interrupt is requested. a deactivate rts command is issued (wr5 bit 1 equals 1) to deactivate the rts signal to turn off the line driver after th e multiple-frame packet is sent. on the scc, the processor must monitor the data line to ensure that the frame has been sent before it issues the deactivate rts command. on the escc, rts can be programmed to deactivate au tomatically after the frame is sent. if the following sequence is performed, additional mon itoring is not required: 1. enable automatic rts deactivation (wr7? bit 2 equals 1). int ext/status ip rca ip ext/status ius ext/status interrupt dma read eof reset highest ius from ext/status handler resetting highest ius from lower priority interrupt clears the eof (rca) interrupt.
ps005308-0609 z80230/z85230/l errata z80230/z85230/l product specification 102 2. enable the crc/flag on unde rrun (wr10 bit 2 equals 0). 3. issue a deactivate rts command in the transmit underrun isr. the rts signal deactivates automatically after the closing flag disappears. the automatic rts deactivation command works for a single frame and for two consecutive frames back-to-back . this command does not work with more than two back- to-back frames. in the latter condition, if the deactivate rts command is issued at the beginning of the transmit underrun isr. rts is deactivated after the crc is gone, but before the clos - ing flag is sent. the final frame is not concluded, and is corrupted. rts problem solutions a workaround for the rts problem is not to send back-t o-back frames. idle time is inserted between frames. there is, however, a limitation to this workaround in that the system throughput is reduced by the idle time inserted between the frames. figure 36 displays automatic rts deactivation. figure 36. automatic rts deactivation automatic txd forced hi gh problem description if wr10 is programmed with bits 6 and 5 equa l to 01 (nrzi), bit 3 equals 1 (mark idle) and wr4 bits 5 and 4 equal 10 (sdlc), the txd pin is forced high after detecting the last bit of the closing flag at the falling edge of txc. this feature does not work if back-to- rts frame n-1 frame n txd flag frame n-1 crc flag frame n crc flag rts frame n-1 frame n txd flag frame n-1 crc flag frame n crc flag rts deactivates correctly (after the closing flag) if only one back-to- back frame is sent. rts deactivates too soon, after the crc, but before the closing flag if more than two back-to-back frames are sent. rts must deactivate after the last closing flag is gone.
ps005308-0609 z80230/z85230/l errata z80230/z85230/l product specification 103 back frames are sent. the txd output is automa tically forced high for eight bit-times and the first byte of the second frame is corrupted . in a multiple-frame transmission, a zero (0) bit is inserted before the ope ning flag of the second frame. automatic txd forced hi gh problem solutions send back-to-back frames in flag idle mode , because the automatic txd forced high feature creates problems only if al l the following conditions are true: ? back-to-back frame transmission ? nrzi ? mark idle setting the system in flag idle mode (wr10 b it 3 equals 0) in frame transmission allows back-to-back frames to be sent without any data corruption. sdlc fifo overflow problem description in sdlc mode, bit 7 of rr7 (fifo overflow stat us bit) is set if an 11th frame ends while the fifo is full (that is, ten frames have accu mulated in the status fifo and have not yet been read by the processor). under this circ umstance, the status fifo is locked and no data can be written to the status fifo until bit 7 of rr7 is reset. if the escc is set up in anti-lock mode (that is, the sdkc fifo is used when receive interrupts on special c ondition only is enabled), the on ly method of resetting bit 7 of rr7(the fifo overflow bit) is to rese t and set wr15 bit 2 (sdlc fifo enable bit). this action causes the sdlc fifo to reset an d all the sdlc frame information is lost. with no anti-lock feature, the fifo overflow status bit is reset if the sdlc fifo is read. if the escc is in nrzi and mark idle in back -to-back frame transmission, (one the fifo overflow bit rr7 bit 7) is set, the only method of resetting the status is to reset and set wr15 bit 2. this action causes the sdlc fifo to reset and the un processed frame infor - mation stored in the sdlc fifo is lost. sdlc fifo overflow problem solution do not use receive interrupts on special conditio ns only and mark idle if there is a pos - sibility of status fifo overflow. default rr0 value problem description rr7 bit 7, the break/abort status bit, does not always clear after reset. default rr0 value problem solution ignore the first bit 7 value read from rr0 after reset.
ps005308-0609 z80230/z85230/l errata z80230/z85230/l product specification 104 default rr10 value problem description rr10 bit 6, the 2 clock missing bit, is sometim es erroneously set to indicate that the dpll detects a clock edge in two successive tries after hardware reset. default rr10 valu e problem solution ignore the first bit 7 valu e read from rr10 after reset. crc problem description the crc cannot be interpreted from the receive fifo when one or two residue bits are sent. the crc value is received and checked co rrectly but is not loaded to the receive fifo. the two types of crc pr oblems are described below: ? two residue bits (residue code is 000 ) the last three bytes of the receive fifo read: bits 6 and 7 of the crc are lost. ? one residue bit (residue code is 111 ) the last three bytes of the receive fifo read: bit 7 of the crc is lost. the crc is received and loaded into the receive fifo in other situations (that is, the 0, 3, 4, 5, 6, and 7 residue bits). the residue code, rr1 bits 3, 2, and 1, is re ported independently of the number of residue bits sent. crc problem solution ignore the crc value read from the receive fifo if one or two residue bits are sent. d7 d6 d5 d4 d3 d2 d1 d0 c5 c4 c3 c2 c1 c0 d9 d8 c15 c14 c13 c12 c11 c10 c9 c8 d7 d6 d5 d4 d3 d2 d1 d0 c6 c5 c4 c3 c2 c1 c0 d8 c15 c14 c13 c12 c11 c10 c9 c8
ps005308-0609 package information z80230/z85230/l product specification 105 package information figure 37 displays the 40-pin du al-inline package (dip). figure 37. 40-pin dip package diagram 1 20 21 40 e1 d s b b1 q1 a1 a2 l e ea symbol millimeter inch min max min max a1 0.51 0.81 .020 .032 a2 3.25 3.43 .128 .135 b 0.38 0.53 .015 .021 b1 1.02 1.52 .040 .060 c 0.23 0.38 .009 .015 d 52.07 52.58 2.050 2.070 e 15.24 15.75 .600 .620 e1 13.59 14.22 .535 .560 2.54 typ .100 typ ea 15.49 16.51 .610 .650 l 3.18 3.81 .125 .150 q1 1.52 1.91 .060 .075 s 1.52 2.29 .060 .090 controlling dimensions: inch e e c
ps005308-0609 package information z80230/z85230/l product specification 106 figure 38 displays the 44-pin plastic leaded chip carrier (plcc) package. figure 38. 44-pin plcc package diagram 0.020/0.014 0.045/0.025 0.032/0.026 r 1.14/0.64 .028/.020 0.51/0.36 0.81/0.66 d2 e e1 3. dimension : mm 2. leads are coplanar within 0.004". 1. controlling dimension : inch notes: 17 18 inch 29 28 d d1 61 7 45 40 39 a1 a 0.71/0.51 1.321/1.067 0.052/0.042 e dim. from center to center of radii ch m d/e 0.650 0.600 d1/e1 e d2 1.27 bsc 16.51 15.24 16.00 16.66 0.050 bsc 0.630 0.656 min 0.168 0.095 0.685 symbol a1 a millimeter 4.27 2.41 17.40 min 2.92 17.65 4.57 max 0.115 0.695 0.180 inch max m
ps005308-0609 ordering information z80230/z85230/l product specification 107 ordering information order the required escc from z ilog using the following part details. for more informa - tion on ordering, consult your local zilog sales offices. the zilog website ( www.zilog.com ) lists all the regional offices and pr ovides additional pr oduct information. z8523l (3.3v) z85230 (5v) z8523l available packages 8 mhz z8523l z8523l08vsg z8523l08veg 10 mhz z8523l z8523l10vsg z8523l10veg 16 mhz z8523l z8523l16vsg z8523l16veg z85230 available packages 8 mhz z85230 z8523008psg z8523008vsg z8523008peg z8523008veg 10 mhz z85230 z8523010psg z8523010vsg z8523010peg z8523010veg 16 mhz z85230 z8523016psg z8523016vsg z8523016peg Z8523016VEG 20 mhz z85230 z8523020psg z8523020vsg
ps005308-0609 ordering information z80230/z85230/l product specification 108 z80230 part number suffix designation z80230 available packages 10 mhz z80230 z8023010psg z8023010vsg 16 mhz z80230 z8023016psg z8023016vsg z 80230 16 p s g environmental flow g = green plastic packaging compound temperature e = -40 ? c to +100 ? c s = 0 ? c to +70 ? c package p = plastic dip (pdip) v = plastic lcc (plcc) speed 8 = 8.0 mhz 10 = 10.0 mhz 16 = 16.384 mhz 20 = 20 mhz product number zilog prefix
ps005308-0609 customer support z80230/z85230/l product specification 112 customer support for answers to technical questions about the product, documentation, or any other issues with zilog?s offerings, please visit zilog?s knowledge base at ? http://www.zilog.com/kb. for any comments, detail technical questions, or reporting problems, please visit zilog?s technical support at http://support.zilog.com .
z80230/z85230/l ps005308-0609 p r e l i m i n a r y index 108 index a abort character 18 absolute maximum ratings 75 ac characteristics 78 ac characteristics table, z85230 90 ac characteristics, z85230 87 asynchronous receive mode 4 auto echo and logical loopback 21 auto enable 4 automatic eom reset 28 b baud rate generator 19 bisync 4, 16 block transfer, cpu/dma 15 c capacitance 76 character abort 18 eop 18 code nrz 18 nrzi 18 command reset highest ius 28 reset tx crc generator 28 reset tx/underrun latch 28 counter transmit clock 5 crc problem description 104 solution 104 crc reception in sdlc mode 26 customer feedback form 112 d data communications capabilities 15 data encoding 20 dc characteristics 77 default rr0 value problem description 103 solution 103 default rr10 value problem description 104 solution 104 device type identification 24 diagram 40-pin dip package 105 44-pin plcc package 106 automatic rts deactivation 102 cycle timing, z85230 89 data encoding methods 20 detecting 5-or 7-bit characters 16 dpll outputs 27 escc protocols 15 general timing, z80230 81 general timing, z85230 94 interrupt acknowledge cycle timing, z80230 72 interrupt acknowledge cycle timing, z85230 74 interrupt acknowledge timing, z80230 80 interrupt acknowledge timing, z85230 89 interrupt priority schedule 13 read cycle timing, z80230 71 read cycle timing, z85230 73 read/write timing, z80230 79 read/write timing, z85230 88 receive data path 9 reset timing, z80230 80 reset timing, z85230 89 resetting highest ius from lower priority 101 sdlc frame status fifo 29 sdlc loop 18 standard and open-d rain test conditions 76 system timing, z80230 86 system timing, z85230 98 transmit data path 8 txip latching 27
z80230/z85230/l ps005308-0609 p r e l i m i n a r y index 109 write cycle timing,z85230 74 z80230 pin assignments 3 z80230 pin functions 2 z85230 pin assignments 3 z85230 pin functions 2 digital phase-locked loop 5, 19 dpll counter tx clock source 27 e encoding, data 20 end of poll (eop) character 18 enhancements receive fifo, 8 bytes 22 transmit fifo, 4 bytes 22 z80230 and z85230 22 eop 18 errata 99 escc programming 32 read registers 53 write registers 32 external synchronization 4 f fifo anti-lock feature 31 enable/disable 30 read operation 30 write operation 31 functional description 8 g general timing characteristics table, z80230 82 general timing table, z85230 95 i identification, device types 24 ie 12 input/output capabilities 9 intack 13 interface timing, z80230 70 internal synchronization 4 interrupt acknowle dge cycle timing z80230 71 z85230 74 interrupts 12 external/status 13, 14 interrupt cknowledge (intack) 13 interrupt enable (ie) 12 interrupt on all receive characters or special re- ceive conditions 14 interrupt on first receive character or special re- ceive condition 14 interrupt on special receive conditions only 14 interrupt pending (ip) 12, 13 interrupt under service (ius) 12, 13 receive 13 receive character available 22 transmit 13 transmit buffer empty 22, 24 tx underrun/eom 28 ius latch 28 ius problem description 99 solutions 100 l latch isu 28 rr0 27 txip 26 local loopback 21 m mark idle 26 mode 1x 18 asynchronous receive 4 auto echo 21 request on transmit 24 sdlc 17
z80230/z85230/l ps005308-0609 p r e l i m i n a r y index 110 sdlc loop 18 sdlc status fifo 19 synchronous 16 monosync 4, 16 n no vector (nv) 28 nv 28 o ordering information 107 p package information 105 part number descriiption 108 pin assignments z80230 3 z85230 3 pin descriptions 1 pin functions z80230 2 z85230 2 pins, common ctsa 4 ctsb 4 dcda 4 dcdb 4 dtr/reqa 4 dtr/reqb 4 iei 5 ieo 5 int 6 intack 6 pclk 5 rtsa 4 rtsb 4 rtxca 5 rtxcb 5 rxda 5, 16 rxdb 5, 16 synca 4 syncb 4 trxca 5 trxcb 5 txda 5 txdb 5 w/reqa 5 w/reqb 5 pins, z80230 exclusive a7-a0 6 as 7 cs0 7 cs1 7 ds 7 r/w 6 pins, z85230 exclusive ce 6 channels a/b 6 d/c 6 d7-d0 6 rd 6 wr 6 polynomial, sdlc crc 17 r ratings, absolute maximum 75 read cycle timing z80230 71 z85230 73 read register (rr) 10 read registers 53 receive conditions 14 request on receive 22 request on transmit 22 request on transmit mode 24 reset highest ius command 28 reset tx crc gene rator command 28 reset tx/underrun eom latch 28 rr 10 rr0 latch 27 rts problem description 101 solutions 102
z80230/z85230/l ps005308-0609 p r e l i m i n a r y index 111 s sdlc crc polynomial 17 fifo frame status enhancement 28 loop mode 18 mode, crc reception 26 mode, txd forced high 26 status fifo 19 status fifo anti-lock feature 31 transmit data interrupt response 28 sdlc fifo overflow problem description 103 solutions 103 sdlc mode 17 software interrupt acknowledge 28 standard test conditions 75 synchronization external 4 internal 4 synchronous modes 16 system timing characteristics table, z85230 98 t timing, z85230 72 transmit buffer empty interrupt 22 transmit clock counter 5 tx underrun/eom interrupt 28 txd forced high in sdlc mode 26 txd forced high problem description 102 solutions 103 txip latch 26 v vector includes status (vis) 28 vis 28 w wr 10 wr7? 9, 23 write cycle timing z80230 70 z85230 73 write register (wr) 10 write register 7 prime (wr&?) 23 write register 7 prime (wr7?) 9 bit 0 25 bit 1 25 bit 2 25 bit 3 25 bit 4 24 bit 5 24 bit 6 24 bit 7 24 write registers 32

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